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US Patent 10319739 Accommodating imperfectly aligned memory holes

Patent 10319739 was granted and assigned to Applied Materials on June, 2019 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
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Current Assignee
Applied Materials
Applied Materials
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Date Filed
January 29, 2018
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Date of Patent
June 11, 2019
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Patent Applicant
Applied Materials
Applied Materials
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Patent Application Number
15882454
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Patent Citations
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US Patent 10062578 Methods for etch of metal and metal-oxide films
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US Patent 10062579 Selective SiN lateral recess
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US Patent 10062587 Pedestal with multi-zone temperature control and multiple purge capabilities
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US Patent 10062585 Oxygen compatible plasma source
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US Patent 10026621 SiN spacer profile patterning
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US Patent 10032606 Semiconductor processing with DC assisted RF power for improved control
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US Patent 10043674 Germanium etching systems and methods
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US Patent 10043684 Self-limiting atomic thermal etching systems and methods
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US Patent 10049891 Selective in situ cobalt residue removal
Patent Citations Received
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US Patent 11930637 Confined charge trap layer
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US Patent 11276590 Multi-zone semiconductor substrate supports
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US Patent 11682560 Systems and methods for hafnium-containing film removal
0
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US Patent 11361939 Semiconductor processing chamber for multiple precursor flow
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US Patent 11417534 Selective material removal
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US Patent 10529737 Accommodating imperfectly aligned memory holes
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US Patent 10541113 Chamber with flow-through source
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US Patent 10541246 3D flash memory cells which discourage cross-cell electrical tunneling
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US Patent 10546729 Dual-channel showerhead with improved profile
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US Patent 10573496 Direct outlet toroidal plasma source
•••
Patent Inventor Names
Vinod R. Purayath
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10319739
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Patent Primary Examiner
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John P. Dulka
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