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US Patent 10290328 Memory module with packages of stacked memory chips

Patent 10290328 was granted and assigned to Netlist, Inc on May, 2019 by the United States Patent and Trademark Office.

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Patent Applicant
Netlist, Inc
Netlist, Inc
1
Current Assignee
Netlist, Inc
Netlist, Inc
1
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
102903281
Patent Inventor Names
Hyun Lee1
Date of Patent
May 14, 2019
1
Patent Application Number
156020991
Date Filed
May 22, 2017
1
Patent Citations Received
‌
US Patent 11972121 Load-reduced DRAM stack
2
‌
US Patent 10902886 Memory module with buffered memory packages
Patent Primary Examiner
‌
Huan Hoang
1
Patent abstract

A memory module is operable in a computer system to communicate with a system memory controller via a command/address bus and a data bus. The memory module comprises a register device coupled to the command/address bus, and a plurality of DRAM packages coupled to the data bus and to the register device via a set of module control lines. Each respective DRAM package comprises stacked array dies and a control die. The control die includes data signal conduits and control signal conduits. In response to the memory module receiving a set of command/address signals from the system memory controller, the register device outputs control signals, and the control die configures the data signal conduits in accordance with the control signals to enable respective bits of one or more data signals to be communicated between a selected die among the stacked dies and the system memory controller.

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