Is a
Patent attributes
Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
Date of Patent
May 7, 2019
Patent Application Number
15945165
Date Filed
April 4, 2018
Patent Citations Received
0
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Patent Primary Examiner
Patent abstract
A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.
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