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US Patent 10283356 Semiconductor wafer comprising a monocrystalline group-IIIA nitride layer

Patent 10283356 was granted and assigned to Siltronic on May, 2019 by the United States Patent and Trademark Office.

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Patent abstract

Problems associated with the mismatch between a silicon substrate and a group-IIIA nitride layer are addressed by employing a silicon substrate processed to have a surface comprising closely spaced tips extending from the surface, depositing a group-IIIB silicide layer on the tips, then depositing a group-IIIB nitride layer, and then depositing a group-IIIA nitride.

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Patent Inventor Names
Maik Haeberlen0
Marvin Zoellner0
Sarad Bahadur Thapa0
Thomas Schroeder0
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=102833560
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Infobox
Is a
Patent
Patent
0
Patent Applicant
Siltronic
Siltronic
0
Current Assignee
Siltronic
Siltronic
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
102833560
Date of Patent
May 7, 2019
0
Patent Application Number
155475290
Date Filed
January 15, 2016
0
Official Website
https://pdfpiw.uspto.gov/.piw?Docid=102833560
Patent Citations Received
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US Patent 11515408 Rough buffer layer for group III-V devices on silicon
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Patent Primary Examiner
‌
Calvin Y Choi
0
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edited on 30 Nov, 2022
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Infobox
Patent Citations Received
‌
US Patent 11515408 Rough buffer layer for group III-V devices on silicon
0
Edits on 18 Jun, 2022
"Entity importer update"
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Website URL
https://pdfpiw.uspto.gov/.piw?Docid=10283356
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 US Patent 10283356 Semiconductor wafer comprising a monocrystalline group-IIIA nitride layer

Infobox
Is a
Patent
Patent
Patent applicant
Siltronic
Siltronic
Current assignee
Siltronic
Siltronic
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10283356
Date of patent
May 7, 2019
Patent application number
15547529
Date Filed
January 15, 2016
Patent primary examiner
‌
Calvin Y Choi

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