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US Patent 10277236 Asynchronous successive approximation analog-to-digital converter and related methods and apparatus

Patent 10277236 was granted and assigned to Butterfly Network, Inc. on April, 2019 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
‌
Butterfly Network, Inc.
Current Assignee
‌
Butterfly Network, Inc.
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10277236
Patent Inventor Names
Kailiang Chen0
Tyler S. Ralston0
Date of Patent
April 30, 2019
Patent Application Number
15979883
Date Filed
May 15, 2018
Patent Citations
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US Patent 10014871 Asynchronous successive approximation analog-to-digital converter and related methods and apparatus
0
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US Patent 10050639 Partially asynchronous clock scheme for SAR ADC
0
Patent Citations Received
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US Patent 11275161 Ultrasound receiver circuitry and related apparatus and methods
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US Patent 11921240 Symmetric receiver switch for ultrasound devices
0
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US Patent 11863133 Trans-impedance amplifier for ultrasound device and related apparatus and methods
0
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US Patent 10624613 Ultrasound signal processing circuitry and related apparatus and methods
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US Patent 10707886 Asynchronous successive approximation analog-to-digital converter and related methods and apparatus
0
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US Patent 11558062 Methods and apparatuses for turning on and off an ADC driver in an ultrasound device
0
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US Patent 11573309 Time gain compensation circuit and related apparatus and methods
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US Patent 11662447 Trans-impedance amplifier (TIA) for ultrasound devices
0
Patent Primary Examiner
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Peguy Jean Pierre
Patent abstract

An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.

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