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US Patent 10199354 Die sidewall interconnects for 3D chip assemblies

Patent 10199354 was granted and assigned to Intel on February, 2019 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
Current Assignee
Intel
Intel
Date Filed
December 20, 2016
Date of Patent
February 5, 2019
Patent Applicant
Intel
Intel
Patent Application Number
15385673
Patent Citations Received
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US Patent 11495484 3D semiconductor devices and structures with at least two single-crystal layers
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US Patent 11508605 3D semiconductor memory device and structure
0
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US Patent 11515413 3D semiconductor device and structure with memory
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US Patent 12136562 3D semiconductor device and structure with single-crystal layers
0
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US Patent 11476181 3D semiconductor device and structure with metal layers
‌
US Patent 11482440 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
‌
US Patent 11487928 Automation for monolithic 3D devices
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US Patent 11482438 Methods for producing a 3D semiconductor memory device and structure
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US Patent 11482439 Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
‌
US Patent 12094965 3D semiconductor device and structure with metal layers and memory cells
0
•••
Patent Inventor Names
Mitul Modi
0
Digvijay A. Raorane
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10199354
Patent Primary Examiner
‌
Dung Le

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