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US Patent 10096607 Three-dimensional stacked junctionless channels for dense SRAM
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Patent
Date Filed
May 24, 2017
Date of Patent
October 9, 2018
Patent Application Number
15603572
Patent Citations Received
US Patent 10461154 Bottom isolation for nanosheet transistors on bulk substrate
US Patent 10573561 Formation of stacked nanosheet semiconductor devices
US Patent 10483166 Vertically stacked transistors
US Patent 10930563 Formation of stacked nanosheet semiconductor devices
US Patent 10896851 Vertically stacked transistors
US Patent 10373942 Logic layout with reduced area and method of making the same
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10096607
Patent Primary Examiner
Minh-Loan Tran
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