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US Patent 10055533 Visualization of analysis process parameters for layout-based checks

Patent 10055533 was granted and assigned to Mentor Graphics on August, 2018 by the United States Patent and Trademark Office.

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Is a
Patent
Patent

Patent attributes

Patent Applicant
Mentor Graphics
Mentor Graphics
Current Assignee
Mentor Graphics
Mentor Graphics
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10055533
Date of Patent
August 21, 2018
Patent Application Number
14716775
Date Filed
May 19, 2015
Patent Citations Received
‌
US Patent 10885258 Fixing ESD path resistance errors in circuit design layout
Patent Primary Examiner
‌
Leigh Garbowski
Patent abstract

Techniques and mechanisms for marking the parameters of a circuit analysis process for visual identification are disclosed. The visually-identified parameters can then be employed with the results of the circuit analysis to debug the layout design.

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