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US Patent 10042588 Electronic device and operating method thereof

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
March 23, 2017
Date of Patent
August 7, 2018
Patent Application Number
15467374
Patent Citations Received
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US Patent 11948635 Memory device current limiter
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US Patent 10971680 Multi terminal device stack formation methods
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US Patent 11621293 Multi terminal device stack systems and methods
0
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US Patent 11437099 Memory device current limiter
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US Patent 10347314 Method and apparatus for bipolar memory write-verify
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US Patent 10360962 Memory array with individually trimmable sense amplifiers
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US Patent 10395711 Perpendicular source and bit lines for an MRAM array
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US Patent 10395712 Memory array with horizontal source line and sacrificial bitline per virtual source
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US Patent 10411185 Process for creating a high density magnetic tunnel junction array test platform
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US Patent 10446744 Magnetic tunnel junction wafer adaptor used in magnetic annealing furnace and method of using the same
•••
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10042588
Patent Primary Examiner
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Richard Elms

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