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US Patent 10032627 Method for forming stacked nanowire transistors

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Is a
Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10032627
Date of Patent
July 24, 2018
Patent Application Number
14942546
Date Filed
November 16, 2015
Patent Citations Received
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US Patent 12125915 Source/drain features of multi-gate devices
0
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US Patent 11482594 Semiconductor devices with backside power rail and method thereof
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US Patent 11489078 Lightly-doped channel extensions
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US Patent 11508736 Method for forming different types of devices
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US Patent 12107169 Contact structure for stacked multi-gate device
0
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US Patent 12125852 Multi-gate transistors with backside power rail and reduced gate-drain capacitance
0
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US Patent 11462612 Semiconductor device structure
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US Patent 11233005 Method for manufacturing an anchor-shaped backside via
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Patent Primary Examiner
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Joseph C. Nicely
Patent abstract

A method includes forming a first semiconductor stack using an epitaxial growth process, the first semiconductor stack comprising a first plurality of semiconductor layers alternating with a second plurality of semiconductor layers, the first plurality of semiconductor layers comprising a first semiconductor material and the second plurality of semiconductor layers comprising a second semiconductor material that is different than the first semiconductor material. The method further includes patterning the first semiconductor stack to form a set of semiconductor stack features, forming isolation features between the semiconductor stack features, removing at least one of the semiconductor stack features, thereby forming at least one trench, and forming, within the trench, a second semiconductor stack using an epitaxial growth process, the second semiconductor stack having different characteristics than the first semiconductor stack.

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