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US Patent 10008490 High speed interface protection apparatus

Patent 10008490 was granted and assigned to Analog Devices on June, 2018 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
Analog Devices
Analog Devices
Current Assignee
Analog Devices
Analog Devices
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10008490
Patent Inventor Names
Jonathan Pfeifer0
Javier Alejandro Salcedo0
Date of Patent
June 26, 2018
Patent Application Number
15614048
Date Filed
June 5, 2017
Patent Citations Received
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US Patent 11362203 Electrical overstress protection for electronic systems subject to electromagnetic compatibility fault conditions
0
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US Patent 11502078 Latch-up immunization techniques for integrated circuits
0
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US Patent 10700056 Apparatus for automotive and communication systems transceiver interfaces
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US Patent 10854596 CMOS RF power limiter and ESD protection circuits
0
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US Patent 10930650 Latch-up immunization techniques for integrated circuits
‌
US Patent 11342323 High voltage tolerant circuit architecture for applications subject to electrical overstress fault conditions
‌
US Patent 11469717 Microwave amplifiers tolerant to electrical overstress
0
‌
US Patent 10249609 Apparatuses for communication systems transceiver interfaces
Patent Primary Examiner
Patent abstract

The disclosed technology relates to electronics, and more particularly, to protection devices that protect circuits from transient electrical events such as electrical overstress/electrostatic discharge. A protection device includes a semiconductor substrate having formed therein at least two wells and a deep well underlying and contacting the at least two wells. The device additionally includes a first PN diode formed in one of the at least two wells and having a first heavily doped region of a first conductivity type and a first heavily doped region of a second conductivity type, and includes a second PN diode formed in one of the at least two wells and having a second heavily doped region of the first conductivity type and a second heavily doped region of the second conductivity type. The device additionally includes a first PN diode and the second PN diode are electrically shorted by an electrical shorting structure to form a first plurality of serially connected diodes having a threshold voltage. The device further includes a PNPN silicon-controlled rectifier (SCR) having a trigger voltage and comprising the first heavily doped region of the first conductivity type, the at least two wells, the deep well, and the second heavily doped region of the second conductivity type.

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