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Phallaka Kik

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Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
Edits made to:
Infobox (-368 properties)
Infobox
Patent primary examiner of
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US Patent 11168380 Method of structural cold working-residual compressive stress distribution quantitative matching design
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US Patent 7093218 Incremental, assertion-based design verification
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US Patent 7096442 Optimizing IC clock structures by minimizing clock uncertainty
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US Patent 7096443 Method for determining the critical path of an integrated circuit
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US Patent 7096445 Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit
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US Patent 7096451 Mesh plane generation and file storage
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US Patent 7096452 Method and device for checking lithography data
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US Patent 7100128 Zone tree method and mechanism
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US Patent 7100141 Technology mapping technique for fracturable logic elements
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US Patent 7100142 Method and apparatus for creating a mask-programmable architecture from standard cells
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US Patent 7103863 Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system
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US Patent 7103864 Semiconductor device, and design method, inspection method, and design program therefor
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US Patent 7107555 Method and apparatus for designing high-frequency circuit, and display method for use in designing high-frequency circuit
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US Patent 7107559 Method of partitioning an integrated circuit design for physical design verification
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US Patent 7107564 Method and apparatus for routing a set of nets
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US Patent 7107566 Programmable logic device design tools with gate leakage reduction capabilities
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US Patent 7107567 Electronic design protection circuit
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US Patent 7111277 System and method for lithography simulation
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US Patent 7114145 System and method for lithography simulation
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US Patent 7117460 Method for physical parameter extraction for transistor model
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US Patent 7117465 Application of the retimed normal form to the formal equivalence verification of abstract RTL descriptions for pipelined designs
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US Patent 7117467 Methods for optimizing package and silicon co-design of integrated circuit
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US Patent 7117477 System and method for lithography simulation
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US Patent 7117478 System and method for lithography simulation
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US Patent 7120884 Mask revision ID code circuit
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US Patent 7120886 Device for determining the mask version utilized for each metal layer of an integrated circuit
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US Patent 7120888 Method, system and storage medium for determining circuit placement
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US Patent 7120895 System and method for lithography simulation
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US Patent 7127688 Method and apparatus for determining interactive electromagnetic effects among conductors of a multi-layer circuit
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US Patent 7131096 Method of automatically routing nets according to current density rules
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US Patent 7143376 Method and apparatus for design verification with equivalency check
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US Patent 7143381 Resonance reduction arrangements
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US Patent 7143390 Method for creating alternating phase masks
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US Patent 7146589 Reducing equivalence checking complexity using inverse function
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US Patent 7149997 Routing with frame awareness to minimize device programming time and test cost
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US Patent 7155694 Trial placement system with cloning
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US Patent 7159202 Methods, apparatus and computer program products for generating selective netlists that include interconnection influences at pre-layout and post-layout design stages
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US Patent 7165231 Method and system for incremental behavioral validation of digital design expressed in hardware description language
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US Patent 7174520 Characterization and verification for integrated circuit designs
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US Patent 7174525 Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
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US Patent 7188329 Computer-assisted electronic component schematic linking method
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US Patent 7191417 Method and apparatus for optimization of digital integrated circuits using detection of bottlenecks
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US Patent 7191425 Method and apparatus for inserting extra tracks during library architecture migration
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US Patent 7191426 Method and apparatus for performing incremental compilation on field programmable gate arrays
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US Patent 7194705 Simulation of integrated circuitry within a high-level modeling system using hardware description language circuit descriptions
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US Patent 7200824 Performance/power mapping of a die
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US Patent 7200825 Methodology of quantification of transmission probability for minority carrier collection in a semiconductor chip
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US Patent 7200831 Semiconductor integrated circuit wiring design method and semiconductor integrated circuit
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US Patent 7200835 Method of locating sub-resolution assist feature(s)
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US Patent 7203916 System, method and program product for positioning I/O pads on a chip
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US Patent 7203918 Delay and signal integrity check and characterization
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US Patent 7207019 Test circuit inserting method and apparatus for a semiconductor integrated circuit
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US Patent 7207020 Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool
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US Patent 7213223 Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatism
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US Patent 7216309 Method and apparatus for model-order reduction and sensitivity analysis
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US Patent 7216313 Incorporation of uncertainty information in modeling a characteristic of a device
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US Patent 7216315 Error portion detecting method and layout method for semiconductor integrated circuit
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US Patent 7216320 Delta-geometry timing prediction in integrated circuit fabrication
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US Patent 7219314 Application-specific methods for testing molectronic or nanoscale devices
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US Patent 7219318 System and method for verifying a layout of circuit traces on a motherboard
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US Patent 7219322 Multiple propagation speeds of signals in layered circuit apparatus
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US Patent 7219325 Exploiting unused configuration memory cells
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US Patent 7231626 Method of implementing an engineering change order in an integrated circuit design by windows
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US Patent 7234122 Three-dimensional interconnect resistance extraction using variational method
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US Patent 7237211 Method for reducing the evaluation outlay in the monitoring of layout changes for semiconductor chips
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US Patent 7237214 Method and apparatus for circuit partitioning and trace assignment in circuit design
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US Patent 7237216 Clock gating approach to accommodate infrequent additional processing latencies
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US Patent 7240306 Integrated circuit layout critical area determination using Voronoi diagrams and shape biasing
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US Patent 7243313 System and method for reducing the size of RC circuits
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US Patent 7246341 Byte slice based DDR timing closure
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US Patent 7249334 Method for generating timing constraints of logic circuit
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US Patent 7254801 Synthesis aware placement: a novel approach that combines knowledge of possible resynthesis
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US Patent 7260795 Method and apparatus for integrating a simulation log into a verification environment
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US Patent 7260803 Incremental dummy metal insertions
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US Patent 7275224 Method for providing an area optimized binary orthogonality checker
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US Patent 7278122 Hardware/software design tool and language specification mechanism enabling efficient technology retargeting and optimization
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US Patent 7281227 Method and device for the computer-aided design of a supply network
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US Patent 7281229 Method to create an alternate integrated circuit layout view from a two dimensional database
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US Patent 7284225 Embedding a hardware object in an application system
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US Patent 7284227 Method and system for generating implementation files from a high level specification
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US Patent 7287240 Designing method and device for phase shift mask
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US Patent 7290233 Method for netlist path characteristics extraction
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US Patent 7290242 Pattern generation on a semiconductor surface
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US Patent 7293247 Encapsulating parameterized cells (pcells)
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US Patent 7293250 Method of modeling physical layout of an electronic component in channel simulation
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US Patent 7299427 Radio prototyping system
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US Patent 7299431 Method for tracing paths within a circuit
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US Patent 7299437 Method and apparatus for detecting timing exception path and computer product
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US Patent 7299445 Nonlinear receiver model for gate-level delay calculation
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US Patent 7302659 System and method for unfolding/replicating logic paths to facilitate propagation delay modeling
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US Patent 7305632 Method for designing arithmetic device allocation
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US Patent 7305639 Method and apparatus for specifying multiple voltage domains and validating physical implementation and interconnections in a processor chip
‌
US Patent 7305642 Method of tiling analog circuits
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US Patent 7305647 Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage
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US Patent 7308656 Method and apparatus for generating a boundary scan description and model
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US Patent 7308666 Method and an apparatus to improve hierarchical design implementation
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US Patent 7308669 Use of redundant routes to increase the yield and reliability of a VLSI layout
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US Patent 7313773 Method and device for simulator generation based on semantic to behavioral translation
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US Patent 7315992 Electro-migration (EM) and voltage (IR) drop analysis of integrated circuit (IC) designs
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US Patent 7315995 Semiconductor integrated circuit designing method and program
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US Patent 7315999 Method and apparatus for identifying assist feature placement problems
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US Patent 7320115 Method for identifying a physical failure location on an integrated circuit
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US Patent 7320118 Delay analysis device, delay analysis method, and computer product
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US Patent 7325210 Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect
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US Patent 7328416 Method and system for timing modeling for custom circuit blocks
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US Patent 7331026 Method and system for generating an initial layout of an integrated circuit
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US Patent 7331030 Method to unate a design for improved synthesizable domino logic flow
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US Patent 7331031 Method for describing and deploying design platform sets
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US Patent 7331032 Computer-aided design system to automate scan synthesis at register-transfer level
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US Patent 7334203 RaceCheck: a race logic analyzer program for digital integrated circuits
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US Patent 7334205 Optimization of die placement on wafers
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US Patent 7340713 Method and apparatus for determining a proximity correction using a visible area model
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US Patent 7346862 Method and apparatus for optimizing a logic network in a digital circuit
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US Patent 7346868 Method and system for evaluating design costs of an integrated circuit
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US Patent 7346869 Power network analyzer for an integrated circuit design
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US Patent 7346876 ASIC having dense mask-programmable portion and related system development method
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US Patent 7350167 Extraction and reduction of capacitor elements using matrix operations
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US Patent 7350171 Efficient statistical timing analysis of circuits
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US Patent 7353473 Modeling small mosfets using ensemble devices
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US Patent 7353474 System and method for accessing signals of a user design in a programmable logic device
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US Patent 7353481 Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit
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US Patent 7356784 Integrated synthesis placement and routing for integrated circuits
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US Patent 7356785 Optimizing IC clock structures by minimizing clock uncertainty
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US Patent 7356793 Genie: a method for classification and graphical display of negative slack timing test failures
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US Patent 7360180 Computer program product, method, and system for hardware model conversion
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US Patent 7360181 Enhanced structural redundancy detection
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US Patent 7360186 Invariant checking
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US Patent 7360195 Block level routing architecture in a field programmable gate array
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US Patent 7363601 Integrated circuit selective scaling
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US Patent 11182526 Methods for engineering integrated circuit design and development
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US Patent 11183830 Methods for detecting an imminent power failure in time to protect local design state
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US Patent 7373623 Method and apparatus for locating circuit deviations
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US Patent 7373624 Method and system for performing target enlargement in the presence of constraints
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US Patent 7373627 Method of designing wiring structure of semiconductor device and wiring structure designed accordingly
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US Patent 7373628 Method of automatically routing nets using a Steiner tree
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US Patent 7376920 Method to monitor critical dimension of IC interconnect
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US Patent 7376921 Methods for tiling integrated circuit designs
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US Patent 7376924 Methods for placement which maintain optimized behavior, while improving wireability potential
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US Patent 7380229 Automatic generation of correct minimal clocking constraints for a semiconductor product
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US Patent 7392501 Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs
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US Patent 7401319 Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design
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US Patent 7404167 Method for improving design window
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US Patent 7404168 Detailed placer for optimizing high density cell placement in a linear runtime
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US Patent 7406673 Method and system for identifying essential configuration bits
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US Patent 7409653 Sub-resolution alignment of images
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US Patent 7409657 Clock tree layout method for semiconductor integrated circuit
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US Patent 7409659 System and method for suppressing crosstalk glitch in digital circuits
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US Patent 7409668 Method for improving via's impedance
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US Patent 7412673 Integrated system noise management—bounce voltage
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US Patent 7412679 Semiconductor integrated circuit and semiconductor integrated circuit manufacturing method
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US Patent 7415685 Method of verifying the power off effect of a design entity at register transfer level and method of modeling the power off effect
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US Patent 7418694 Method for generating test patterns utilized in manufacturing semiconductor device
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US Patent 7421671 Graph pruning scheme for sensitivity analysis with partitions
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US Patent 7426707 Layout design method for semiconductor integrated circuit, and semiconductor integrated circuit
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US Patent 7428716 System and method for statistical timing analysis of digital circuits
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US Patent 7430731 Method for electrochemically fabricating three-dimensional structures including pseudo-rasterization of data
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US Patent 7434187 Method and apparatus to estimate delay for logic circuit optimization
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US Patent 7434192 Techniques for optimizing design of a hard intellectual property block for data transmission
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US Patent 7437691 VLSI artwork legalization for hierarchical designs with multiple grid constraints
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US Patent 7441219 Method for creating, modifying, and simulating electrical circuits over the internet
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US Patent 7444607 Method for correcting timing error when designing semiconductor integrated circuit
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US Patent 7444608 Method and system for evaluating timing in an integrated circuit
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US Patent 7448008 Method, system, and program product for automated verification of gating logic using formal verification
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US Patent 7448016 Pad layouts of a printed circuit board
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US Patent 7448018 System and method for employing patterning process statistics for ground rules waivers and optimization
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US Patent 7454727 Method and Apparatus for Solving Sequential Constraints
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US Patent 7458047 Method of designing layout of semiconductor integrated circuit and apparatus for doing the same
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US Patent 7458050 Methods to cluster boolean functions for clock gating
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US Patent 7458058 Verifying a process margin of a mask pattern using intermediate stage models
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US Patent 7467361 Pipeline high-level synthesis system and method
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US Patent 7467365 Sanity checker for integrated circuits
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US Patent 7469390 Method and software tool for automatic generation of software for integrated circuit processors
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US Patent 7472359 Behavioral transformations for hardware synthesis and code optimization based on Taylor Expansion Diagrams
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US Patent 7472362 Method of minimizing phase noise
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US Patent 7475383 Method of fabricating photo mask
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US Patent 7478352 Method for creating box level groupings of components and connections in a dynamic layout system
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US Patent 7480882 Measuring and predicting VLSI chip reliability and failure
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US Patent 7480890 Method for correcting and configuring optical mask pattern
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US Patent 7484189 Method for searching for potential faults in a layout of an integrated circuit
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US Patent 7484190 Method to optimize the manufacturing of interconnects in microelectronic packages
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US Patent 7484195 Method to improve time domain sensitivity analysis performance
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US Patent 7487477 Parametric-based semiconductor design
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US Patent 7487480 Method for estimating aggregate leakage of transistors
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US Patent 7487484 Method, system and storage medium for determining circuit placement
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US Patent 7493580 Critical path estimating program, estimating apparatus, estimating method, and integrated circuit designing program
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US Patent 7493581 Analytical placement method and apparatus
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US Patent 7493582 Pattern layout and layout data generation method
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US Patent 7493590 Process window optical proximity correction
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US Patent 7496865 OTA-based high-order filters
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US Patent 7496879 Concurrent optimization of physical design and operational cycle assignment
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US Patent 7500210 Chip area optimization for multithreaded designs
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US Patent 7506289 Approach for routing an integrated circuit
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US Patent 7506298 Methods of mapping a logical memory representation to physical memory in a programmable logic device
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US Patent 7509622 Dummy filling technique for improved planarization of chip surface topography
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US Patent 7512911 Method for creating a parameterized cell library dual-layered rule system for rapid technology migration
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US Patent 7516433 Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit
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US Patent 11188697 On-chip memory access pattern detection for power and resource reduction
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US Patent 7519943 Photomask fabrication method
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US Patent 7523433 System and method for automated analysis and hierarchical graphical presentation of application results
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US Patent 7526741 Microfluidic design automation method and system
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US Patent 7526745 Method for specification and integration of reusable IP constraints
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US Patent 7530046 Chip debugging using incremental recompilation
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US Patent 7530047 Optimized mapping of an integrated circuit design to multiple cell libraries during a single synthesis pass
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US Patent 7533358 Integrated sizing, layout, and extractor tool for circuit design
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US Patent 7533359 Method and system for chip design using physically appropriate component models and extraction
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US Patent 7536664 Physical design system and method
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US Patent 7536666 Integrated circuit and method of routing a clock signal in an integrated circuit
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US Patent 7536667 Method of semiconductor device and design supporting system of semiconductor device
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US Patent 7536671 Mask for forming fine pattern and method of forming the same
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US Patent 7539961 Library-based solver for modeling an integrated circuit
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US Patent 7539962 Pattern data correcting method, photo mask manufacturing method, semiconductor device manufacturing method, program and semiconductor device
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US Patent 7539967 Self-configuring components on a device
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US Patent 7539970 Method of manufacturing mask
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US Patent 7546560 Optimization of flip flop initialization structures with respect to design size and design closure effort from RTL to netlist
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US Patent 7549136 System and method for approximating intrinsic capacitance of an IC block
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US Patent 7549140 Method and apparatus for decomposing semiconductor device patterns into phase and chrome regions for chromeless phase lithography
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US Patent 7549142 Method and device for checking lithography data
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US Patent 7549143 Method and device for checking lithography data
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US Patent 7552406 Incorporation of uncertainty information in modeling a characteristic of a device
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US Patent 7552409 Engineering change order process optimization
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US Patent 7555738 Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip
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US Patent 7555741 Computer-aided-design tools for reducing power consumption in programmable logic devices
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US Patent 7562325 Device to cluster Boolean functions for clock gating
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US Patent 7562337 OPC verification using auto-windowed regions
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US Patent 7568177 System and method for power gating of an integrated circuit
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US Patent 7571398 Method for the determination of the quality of a set of properties, usable for the verification and specification of circuits
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US Patent 7571414 Multi-project system-on-chip and its method
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US Patent 7571415 Layout of power device
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US Patent 7574684 Design data creating method, design data creating apparatus and computer readable information recording medium
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US Patent 7577933 Timing driven pin assignment
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US Patent 7584440 Method and system for tuning a circuit
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US Patent 7584444 System and method for external-memory graph search utilizing edge partitioning
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US Patent 7584449 Logic synthesis of multi-level domino asynchronous pipelines
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US Patent 7587697 System and method of mapping memory blocks in a configurable integrated circuit
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US Patent 7590966 Data path for high performance pattern generator
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US Patent 7594206 Fault detecting method and layout method for semiconductor integrated circuit
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US Patent 7594210 Timing variation characterization
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US Patent 7614028 Representation, configuration, and reconfiguration of routing method and system
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US Patent 7620925 Method and apparatus for performing post-placement routability optimization
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US Patent 7634748 Special engineering change order cells
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US Patent 7634754 Simulation of aerial images
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US Patent 7644386 Redundancy structures and methods in a programmable logic device
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US Patent 7650580 Method and apparatus for determining the performance of an integrated circuit
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US Patent 7650585 Implementing a user design in a programmable logic device with single event upset mitigation
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US Patent 7657856 Method and system for parallel processing of IC design layouts
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US Patent 7657860 Method and system for implementing routing refinement and timing convergence
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US Patent 7657863 Pattern area value calculating method, proximity effect correcting method, and charged particle beam writing method and apparatus
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US Patent 7665053 Semiconductor device layout method and layout program
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US Patent 7669151 Methods for reducing power supply simultaneous switching noise
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US Patent 7669171 Prediction model and prediction method for exposure dose
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US Patent 7669174 Pattern generation method and charged particle beam writing apparatus
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US Patent 7673258 Design data creating method, design data creating program product, and manufacturing method of semiconductor device
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US Patent 7673274 Datapipe interpolation device
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US Patent 7676773 Trace optimization in flattened netlist by storing and retrieving intermediate results
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US Patent 7676777 Method and apparatus for supporting verification, and computer product
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US Patent 7681165 Apparatus and methods for congestion estimation and optimization for computer-aided design software
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US Patent 7681173 Mask data generation method and mask
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US Patent 7685542 Method and apparatus for shutting off data capture across asynchronous clock domains during at-speed testing
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US Patent 7685549 Method of constrained aggressor set selection for crosstalk induced noise
‌
US Patent 7689948 System and method for model-based scoring and yield prediction
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US Patent 7689959 Code generator for finite state machines
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US Patent 7694252 Method and system for static verification of multi-voltage circuit design
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US Patent 7694263 Method of wiring data transmission lines and printed circuit board assembly wired using the method
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US Patent 7698670 Method and apparatus for designing semiconductor integrated device using noise current and impedance characteristics of input/output buffers between power supply lines
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US Patent 7703058 Method and system for changing a description for a state transition function of a state machine engine
‌
US Patent 7703062 Semiconductor integrated circuit and method of designing layout of the same
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US Patent 7707534 Circuit board design tool and methods
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US Patent 7707541 Systems, masks, and methods for photolithography
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US Patent 7712056 Characterization and verification for integrated circuit designs
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US Patent 7712060 Method and system for handling assertion libraries in functional verification
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US Patent 7716612 Method and system for integrated circuit optimization by using an optimized standard-cell library
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US Patent 7716617 Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device
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US Patent 7725849 Feature failure correlation
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US Patent 7725854 Nonlinear receiver model for gate-level delay calculation
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US Patent 7725856 Method and apparatus for performing parallel slack computation
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US Patent 7735032 Early HSS Rx data sampling
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US Patent 7735046 E-fuse and method
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US Patent 7735055 Method of creating photo mask data, method of photo mask manufacturing, and method of manufacturing semiconductor device
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US Patent 7739629 Method and mechanism for implementing electronic designs having power information specifications background
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US Patent 7739631 Testing method and method for manufacturing an electronic device
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US Patent 7752585 Method, apparatus, and computer program product for stale NDR detection
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US Patent 7752592 Scheduler design to optimize system performance using configurable acceleration engines
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US Patent 7757191 Racecheck: a race logic analyzer program for digital integrated circuits
‌
US Patent 7757194 Method and system for generating implementation files from a high level specification
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US Patent 7779375 Design structure for shutting off data capture across asynchronous clock domains during at-speed testing
‌
US Patent 7793241 Power network analyzer for an integrated circuit design
‌
US Patent 7797650 System and method for testing SLB and TLB cells during processor design verification and validation
‌
US Patent 7797654 Power network analyzer for an integrated circuit design
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US Patent 7797655 Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage
‌
US Patent 7805690 Method for generating compiler, simulation, synthesis and test suite from a common processor specification
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US Patent 7810062 Method for eliminating negative slack in a netlist via transformation and slack categorization
‌
US Patent 7814443 Graph-based pattern matching in L3GO designs
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US Patent 7814454 Selectable device options for characterizing semiconductor devices
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US Patent 7818700 System and method for verification and generation of timing exceptions
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US Patent 7818701 Memory controller with variable zone size
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US Patent 7818704 Capacitive decoupling method and module
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US Patent 7823094 Pseudo-string based pattern recognition in L3GO designs
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US Patent 7823110 Method and system for processing geometrical layout design data
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US Patent 7823114 Method of designing wiring structure of semiconductor device and wiring structure designed accordingly
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US Patent 7836420 Integrated circuit system with assist feature
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US Patent 7840919 Resource mapping of functional areas on an integrated circuit
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US Patent 7844924 Device for reducing the width of graph and a method to reduce the width of graph, and a device for logic synthesis and a method for logic synthesis
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US Patent 7844930 Method and apparatus for circuit partitioning and trace assignment in circuit design
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US Patent 7844935 Wiring design system of semiconductor integrated circuit, semiconductor integrated circuit, and wiring design program
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US Patent 7844939 Mask pattern correction program and system
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US Patent 7844940 Mask set for microarray, method of fabricating mask set, and method of fabricating microarray using mask set
‌
US Patent 7849424 Systems, devices, and methods for controlling electrical and optical properties of transparent conductors
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US Patent 7849427 Auto-router performing simultaneous placement of signal and return paths
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US Patent 7853909 ESD analysis device and ESD analysis program used for designing semiconductor device and method of designing semiconductor device
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US Patent 7853910 Parasitic effects analysis of circuit structures
‌
US Patent 7856612 Lithography mask design through mask functional optimization and spatial frequency analysis
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US Patent 7856613 Method for self-aligned doubled patterning lithography
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US Patent 7861204 Structures including integrated circuits for reducing electromigration effect
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US Patent 7870515 System and method for improved hierarchical analysis of electronic circuits
‌
US Patent 7870517 Method and mechanism for implementing extraction for an integrated circuit design
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US Patent 7873937 System and method for lithography simulation
‌
US Patent 7877719 Fast dual-
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US Patent 7882463 Integrated circuit selective scaling
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US Patent 7882481 Wafer layout optimization method and system
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US Patent 7886240 Modifying layout of IC based on function of interconnect and related circuit and design structure
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US Patent 7886255 Method for design of programmable data processors
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US Patent 7895558 Configuration specification language supporting arbitrary mapping functions for configuration constructs
‌
US Patent 7895560 Continuous flow instant logic binary circuitry actively structured by code-generated pass transistor interconnects
‌
US Patent 7904857 Computer-aided design system to automate scan synthesis at register-transfer level
‌
US Patent 7913195 Method for creating mask layout data, apparatus for creating mask layout data, and method for manufacturing semiconductor device
‌
US Patent 7913197 Method for double patterning lithography
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US Patent 7913204 High-level synthesis apparatus, high-level synthesis system and high-level synthesis method
‌
US Patent 7913209 Determining a cycle basis of a directed graph
‌
US Patent 7913211 Logic cell configuration processing method and program
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US Patent 7913216 Accurate parasitics estimation for hierarchical customized VLSI design
‌
US Patent 7917873 System and method for verification of integrated circuit design
‌
US Patent 7917882 Automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof
‌
US Patent 7921398 System and medium for placement which maintain optimized timing behavior, while improving wireability potential
‌
US Patent 7921399 Method for simplifying tie net modeling for router performance
‌
US Patent 7921402 FPGA circuits and methods considering process variations
‌
US Patent 7926015 Optimization method for fractional-N phased-lock-loop (PLL) system
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US Patent 7926017 Layout method for a chip
‌
US Patent 7930658 Semiconductor integrated circuit device and fabrication method thereof
‌
US Patent 7930662 Methods for automatically generating fault mitigation strategies for electronic system designs
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US Patent 7934190 Multiple amplifier matching over lumped networks of arbitrary topology
‌
US Patent 7941774 Partial timing modeling for gate level simulation
‌
US Patent 7949971 Method and apparatus for on-the-fly minimum power state transition
‌
US Patent 7949975 Apparatus and method of extracting equivalent circuit of T-type transmission circuit
‌
US Patent 7949980 Circuit design tools that support devices with real-time phase-locked loop reconfiguration capabilities
‌
US Patent 7949981 Via density change to improve wafer surface planarity
‌
US Patent 7949983 High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature
‌
US Patent 7958465 Dummy pattern design for reducing device performance drift
‌
US Patent 7958472 Increasing scan compression by using X-chains
‌
US Patent 7962865 System and method for employing patterning process statistics for ground rules waivers and optimization
‌
US Patent 7962866 Method, system, and computer program product for determining three-dimensional feature characteristics in electronic designs
‌
US Patent 7962874 Method and system for evaluating timing in an integrated circuit
‌
US Patent 7962875 Method, apparatus and program for designing circuits
‌
US Patent 7962877 Port assignment in hierarchical designs by abstracting macro logic
‌
US Patent 7962879 VLSI artwork legalization for hierarchical designs with multiple grid constraints
‌
US Patent 7966598 Top level hierarchy wiring via 1×N compiler
‌
US Patent 7971166 Method, system, and program product for automated verification of gating logic using formal verification
‌
US Patent 7971172 IC that efficiently replicates a function to save logic and routing resources
‌
US Patent 7975246 MEEF reduction by elongation of square shapes
‌
US Patent 7975249 Operation timing verifying apparatus and program
‌
US Patent 7979813 Chip-scale package conversion technique for dies
‌
US Patent 7979819 Minterm tracing and reporting
‌
US Patent 7979830 Layout design method for a semiconductor integrated circuit
‌
US Patent 7996803 Automated use of uninterpreted functions in sequential equivalence
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US Patent 7996805 Method of stitching scan flipflops together to form a scan chain with a reduced wire length
‌
US Patent 8006202 Systems and methods for UV lithography
‌
US Patent 8006203 Bulk image modeling for optical proximity correction
‌
US Patent 8006212 Method and system for facilitating floorplanning for 3D IC
‌
US Patent 8010921 System and method for statistical timing analysis of digital circuits
Edits on 8 Dec, 2021
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Golden AI
edited on 8 Dec, 2021
Edits made to:
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US Patent 8010921 System and method for statistical timing analysis of digital circuits
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US Patent 8006212 Method and system for facilitating floorplanning for 3D IC
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US Patent 8006203 Bulk image modeling for optical proximity correction
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US Patent 8006202 Systems and methods for UV lithography
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US Patent 7996803 Automated use of uninterpreted functions in sequential equivalence
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US Patent 7979830 Layout design method for a semiconductor integrated circuit
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US Patent 7979819 Minterm tracing and reporting
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US Patent 7979813 Chip-scale package conversion technique for dies
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US Patent 7975249 Operation timing verifying apparatus and program
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US Patent 7975246 MEEF reduction by elongation of square shapes
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US Patent 7971172 IC that efficiently replicates a function to save logic and routing resources
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US Patent 7966598 Top level hierarchy wiring via 1×N compiler
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US Patent 7962879 VLSI artwork legalization for hierarchical designs with multiple grid constraints
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US Patent 7962877 Port assignment in hierarchical designs by abstracting macro logic
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US Patent 7962875 Method, apparatus and program for designing circuits
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US Patent 7962874 Method and system for evaluating timing in an integrated circuit

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