Log in
Sign up
Golden has been acquired by ComplyAdvantage.Read about it here ⟶
‌

Nitin Parekh

OverviewStructured DataIssuesContributorsActivity

All edits

Edits on 27 Sep, 2022
"rollback to version 26092474"
Megan Gustafson profile picture
Megan Gustafson
edited on 27 Sep, 2022
Edits made to:
Infobox (-2 properties)
Infobox
Facebook URL
https://www.facebook.com/profile.php?id=100070397408558
Twitter URL
https://twitter.com/cllrnitin
Edits on 14 Dec, 2021
"Remove inverse infobox"
Golden AI profile picture
Golden AI
edited on 14 Dec, 2021
Edits made to:
Infobox (-457 properties)
Infobox
Patent primary examiner of
‌
US Patent 11171082 Semiconductor package
‌
US Patent 7087461 Process and lead frame for making leadless semiconductor packages
‌
US Patent 7088007 Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
‌
US Patent 7088008 Electronic package with optimized circuitization pattern
‌
US Patent 7091606 Circuit device and manufacturing method of circuit device and semiconductor module
‌
US Patent 7098518 Die-level opto-electronic device and method of making same
‌
US Patent 7098524 Electroplated wire layout for package sawing
‌
US Patent 7098534 Sacrificial component
‌
US Patent 7102225 Die-up ball grid array package with printed circuit board attachable heat spreader
‌
US Patent 7102227 Passive element chip and manufacturing method thereof, and highly integrated module and manufacturing method thereof
‌
US Patent 7102238 Semiconductor device and manufacturing method thereof
‌
US Patent 7105419 Thin-film semiconductor substrate, method of manufacturing thin-film semiconductor substrate, method of crystallization, apparatus for crystallization, thin-film semiconductor device, and method of manufacturing thin-film semiconductor device
‌
US Patent 7105933 Semiconductor integrated circuit device and manufacturing method of the same
‌
US Patent 7116002 Overhang support for a stacked semiconductor device, and method of forming thereof
‌
US Patent 7119427 Stacked BGA packages
‌
US Patent 7119438 Method of arranging microspheres with liquid, microsphere arranging device, and semiconductor device
‌
US Patent 7122460 Electromigration barrier layers for solder joints
‌
US Patent 7122904 Semiconductor packaging device and manufacture thereof
‌
US Patent 7122908 Electronic device package
‌
US Patent 7125798 Circuit device and manufacturing method of circuit device
‌
US Patent 7126229 Wire-bonding method and semiconductor package using the same
‌
US Patent 7132744 Enhanced die-up ball grid array packages and method for making the same
‌
US Patent 11177193 Reservoir structure and system forming gap for liquid thermal interface material
‌
US Patent 11177237 Manufacturing method of semiconductor package
‌
US Patent 7135415 Insulated structure of a chip array component and fabrication method of the same
‌
US Patent 7135782 Semiconductor module and production method therefor and module for IC cards and the like
‌
US Patent 7135783 Contact etching utilizing partially recessed hard mask
‌
US Patent 7141879 Semiconductor device
‌
US Patent 7145237 Electrode employing nitride-based semiconductor of III-V group compound, and producing method thereof
‌
US Patent 7145241 Semiconductor device having a multilayer interconnection structure and fabrication process thereof
‌
US Patent 7148570 Low resistivity titanium silicide on heavily doped semiconductor
‌
US Patent 7151306 Electronic part, and electronic part mounting element and an process for manufacturing such the articles
‌
US Patent 7151318 Semiconductor component and method for contacting said semiconductor component
‌
US Patent 7154165 Flashless lead frame with horizontal singulation
‌
US Patent 7154181 Semiconductor device and method of manufacturing the same
‌
US Patent 7157744 Surface mount package for a high power light emitting diode
‌
US Patent 7160760 Semiconductor device and a method of manufacturing the same
‌
US Patent 7161239 Ball grid array package enhanced with a thermal and electrical connector
‌
US Patent 7161240 Insitu-cooled electrical assemblage
‌
US Patent 7161244 Microwave device for dissipating or attenuating power
‌
US Patent 7164206 Structure in a microelectronic device including a bi-layer for a diffusion barrier and an etch-stop layer
‌
US Patent 7166918 Semiconductor package assembly and method for electrically isolating modules
‌
US Patent 7166919 Leadless type semiconductor package, and production process for manufacturing such leadless type semiconductor package
‌
US Patent 7166923 Semiconductor device, electro-optical unit, and electronic apparatus
‌
US Patent 7173329 Package stiffener
‌
US Patent 7176566 Semiconductor package assembly and method for electrically isolating modules
‌
US Patent 7180192 Semiconductor device
‌
US Patent 7183580 Electro-optical device, manufacturing method of the same, and electronic apparatus
‌
US Patent 7183644 Integrated circuit package with improved power signal connection
‌
US Patent 7190069 Method and system of tape automated bonding
‌
US Patent 7190082 Low stress flip-chip package for low-K silicon technology
‌
US Patent 7192847 Ultra-thin wafer level stack packaging method
‌
US Patent 7193298 Lead frame
‌
US Patent 7193299 Conductor frame and housing for a radiation-emitting component, radiation-emitting component and display and/or illumination system using radiation-emitting components
‌
US Patent 7193315 Test vehicle grid array package
‌
US Patent 7193327 Barrier structure for semiconductor devices
‌
US Patent 7205653 Fluid cooled encapsulated microelectronic package
‌
US Patent 7208405 Insulating film forming method capable of enhancing adhesion of silicon carbide film, etc. and semiconductor device
‌
US Patent 7208818 Power semiconductor package
‌
US Patent 7208842 Semiconductor chip, mounting structure thereof, and methods for forming a semiconductor chip and printed circuit board for the mounting structure thereof
‌
US Patent 7211897 Semiconductor device and method for fabricating the same
‌
US Patent 7211900 Thin semiconductor package including stacked dies
‌
US Patent 7215000 Selectively encased surface metal structures in a semiconductor device
‌
US Patent 7215012 Space-efficient package for laterally conducting device
‌
US Patent 7215030 Lead-free semiconductor package
‌
US Patent 7215033 Wafer level stack structure for system-in-package and method thereof
‌
US Patent 7224061 Package structure
‌
US Patent 7224075 Methods and systems for attaching die in stacked-die packages
‌
US Patent 7227243 Semiconductor device
‌
US Patent 7227256 Die-up ball grid array package with printed circuit board attachable heat spreader
‌
US Patent 7227257 Cooling micro-channels
‌
US Patent 7227260 Method and system for a pad structure for use with a semiconductor package
‌
US Patent 7230333 Semiconductor package
‌
US Patent 7235867 Semiconductor device with electrically biased die edge seal
‌
US Patent 7235874 Semiconductor device, its manufacturing method, circuit board, and electronic unit
‌
US Patent 7235878 Direct cooling of LEDs
‌
US Patent 7241680 Electronic packaging using conductive interposer connector
‌
US Patent 7242086 Optical semiconductor bare chip, printed wiring board, lighting unit and lighting device
‌
US Patent 7242097 Electromigration barrier layers for solder joints
‌
US Patent 7242102 Bond pad structure for copper metallization having increased reliability and method for fabricating same
‌
US Patent 7245008 Ball grid array package, stacked semiconductor package and method for manufacturing the same
‌
US Patent 7245024 Electronic assembly with reduced leakage current
‌
US Patent 7247942 Techniques for joining an opto-electronic module to a semiconductor package
‌
US Patent 7256073 Semiconductor device and manufacturing method thereof
‌
US Patent 7256482 Integrated circuit chip packaging assembly
‌
US Patent 7259456 Heat dissipation apparatus for package device
‌
US Patent 7262508 Integrated circuit incorporating flip chip and wire bonding
‌
US Patent 7265449 Tape circuit substrate, semiconductor chip package including the same, and liquid crystal display device including the semiconductor chip package
‌
US Patent 7271461 Stackable optoelectronics chip-to-chip interconnects and method of manufacturing
‌
US Patent 7271479 Flip chip package including a non-planar heat spreader and method of making the same
‌
US Patent 7271491 Carrier for wafer-scale package and wafer-scale package including the carrier
‌
US Patent 7274091 Semiconductor device and method of manufacturing a semiconductor device
‌
US Patent 7274098 Chip packaging structure without leadframe
‌
US Patent 7274101 Semiconductor package and method for manufacturing the same
‌
US Patent 7274107 Semiconductor device
‌
US Patent 7276786 Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted
‌
US Patent 7279783 Partitioned integrated circuit package with central clock driver
‌
US Patent 7285445 Direct cooling of LEDs
‌
US Patent 7285845 Lead frame for semiconductor package
‌
US Patent 7285867 Wiring structure on semiconductor substrate and method of fabricating the same
‌
US Patent 7291549 Method and structure to reduce risk of gold embrittlement in solder joints
‌
US Patent 7291906 Stack package and fabricating method thereof
‌
US Patent 7291912 Circuit board
‌
US Patent 7291922 Substrate with many via contact means disposed therein
‌
US Patent 7291930 Input and output circuit of an integrated circuit chip
‌
US Patent 7294912 Semiconductor device
‌
US Patent 7300824 Method of packaging and interconnection of integrated circuits
‌
US Patent 7300860 Integrated circuit with metal layer having carbon nanotubes and methods of making same
‌
US Patent 7301176 Semiconductor light emitting device and fabrication method thereof
‌
US Patent 7301233 Semiconductor chip package with thermoelectric cooler
‌
US Patent 7301240 Semiconductor device
‌
US Patent 7304362 Molded integrated circuit package with exposed active area
‌
US Patent 7304365 Semiconductor device and method of producing the same
‌
US Patent 7304369 Integral charge storage basement and wideband embedded decoupling structure for integrated circuit
‌
US Patent 7304378 Aluminum/ceramic bonding substrate
‌
US Patent 7309648 Low profile, chip-scale package and method of fabrication
‌
US Patent 7309914 Inverted CSP stacking system and method
‌
US Patent 7309917 Multilayer board and a semiconductor device
‌
US Patent 7312512 Interconnect structure with polygon cell structures
‌
US Patent 7312520 Interface module for connecting LSI packages, and LSI-incorporating apparatus
‌
US Patent 7312523 Enhanced via structure for organic module performance
‌
US Patent 7315085 Ball grid array package and method thereof
‌
US Patent 7315086 Chip-on-board package having flip chip assembly structure and manufacturing method thereof
‌
US Patent 7317255 Reliable printed wiring board assembly employing packages with solder joints
‌
US Patent 7319272 Ball assignment system
‌
US Patent 7323361 Packaging system for semiconductor devices
‌
US Patent 7323775 Memory module
‌
US Patent 7327044 Integrated circuit package encapsulating a hermetically sealed device
‌
US Patent 7329946 I/O architecture for integrated circuit package
‌
US Patent 7332449 Method for forming dual damascenes with supercritical fluid treatments
‌
US Patent 7332805 Electronic package with improved current carrying capability and method of forming the same
‌
US Patent 7338891 Semiconductor chip, mounting structure thereof, and methods for forming a semiconductor chip and printed circuit board for the mounting structure thereof
‌
US Patent 7339272 Semiconductor device with scattering bars adjacent conductive lines
‌
US Patent 7348214 Integrated circuit package with improved power signal connection
‌
US Patent 7351641 Structure and method of forming capped chips
‌
US Patent 7358539 Flip-chip light emitting diode with indium-tin-oxide based reflecting contacts
‌
US Patent 7358609 Semiconductor device
‌
US Patent 7361977 Semiconductor assembly and packaging for high current and low inductance
‌
US Patent 11183436 Power module package and packaging techniques
‌
US Patent 7365421 IC chip package with isolated vias
‌
US Patent 7368325 Semiconductor package
‌
US Patent 7375428 Flip-chip bonding structure using multi chip module-deposited substrate
‌
US Patent 7375435 Chip package structure
‌
US Patent 7382049 Chip package and bump connecting structure thereof
‌
US Patent 7385279 Semiconductor device and a method of manufacturing the same
‌
US Patent 7385288 Electronic packaging using conductive interproser connector
‌
US Patent 7391115 Semiconductor device and manufacturing method thereof
‌
US Patent 7394159 Delamination reduction between vias and conductive pads
‌
US Patent 7397138 Semiconductor device
‌
US Patent 7402454 Molded integrated circuit package with exposed active area
‌
US Patent 7402515 Method of forming through-silicon vias with stress buffer collars and resulting devices
‌
US Patent 7405104 Lead frame and method of producing the same, and resin-encapsulated semiconductor device and method of producing the same
‌
US Patent 7405107 Semiconductor device, method and apparatus for fabricating the same
‌
US Patent 7405475 Method and system of tape automated bonding
‌
US Patent 7405478 Substrate package structure and packaging method thereof
‌
US Patent 7408243 High temperature package flip-chip bonding to ceramic
‌
US Patent 7410886 Method for fabricating protective caps for protecting elements on a wafer surface
‌
US Patent 7411285 Low profile stacked semiconductor chip package
‌
US Patent 7413995 Etched interposer for integrated circuit devices
‌
US Patent 7414302 Flashless lead frame with horizontal singulation
‌
US Patent 7416923 Underfill film having thermally conductive sheet
‌
US Patent 7417314 Semiconductor chip assembly with laterally aligned bumped terminal and filler
‌
US Patent 7420286 Reduced inductance in ball grid array packages
‌
US Patent 7422979 Method of forming a semiconductor device having a diffusion barrier stack and structure thereof
‌
US Patent 7423334 Image sensor module with a protection layer and a method for manufacturing the same
‌
US Patent 7429799 Land patterns for a semiconductor stacking structure and method therefor
‌
US Patent 7432590 Ceramic package, assembled substrate, and manufacturing method therefor
‌
US Patent 7436053 Optical device and method for fabricating the same
‌
US Patent 7436062 Semiconductor chip element, semiconductor chip element mounting structure, semiconductor chip element mounting device and mounting method
‌
US Patent 7436074 Chip package without core and stacked chip package structure thereof
‌
US Patent 7439628 Method for improved process latitude by elongated via integration
‌
US Patent 7443027 Electronic device having coalesced metal nanoparticles
‌
US Patent 7443042 Methods and apparatus for wire bonding with wire length adjustment in an integrated circuit
‌
US Patent 7445968 Methods for integrated circuit module packaging and integrated circuit module packages
‌
US Patent 7446396 Stacked integrated circuit leadframe package system
‌
US Patent 7446423 Semiconductor device and method for assembling the same
‌
US Patent 7453152 Device having reduced chemical mechanical planarization
‌
US Patent 7453156 Wire bond interconnection
‌
US Patent 7462509 Dual-sided chip attached modules
‌
US Patent 7462511 Semiconductor device and the method of producing the same
‌
US Patent 7462557 Semiconductor component and method for contracting said semiconductor component
‌
US Patent 7462931 Indented structure for encapsulated devices and method of manufacture
‌
US Patent 7462933 Ball grid array package enhanced with a thermal and electrical connector
‌
US Patent 7462934 Integrated heat sink
‌
US Patent 7468288 Die-level opto-electronic device and method of making same
‌
US Patent 7468544 Structure and process for WL-CSP with metal cover
‌
US Patent 7468560 Semiconductor device with micro connecting elements and method for producing the same
‌
US Patent 7470977 Modular board device, high frequency module, and method of manufacturing same
‌
US Patent 7470984 Perpendicularly oriented electrically active element method and system
‌
US Patent 7473579 Self-aligned wafer level integration system
‌
US Patent 7476981 Electronic module with layer of adhesive and process for producing it
‌
US Patent 7479700 Semiconductor device featuring copper wiring layers of different widths having metal capping layers of different thickness formed thereon, and method for manufacturing the same
‌
US Patent 7479702 Composite conductive film and semiconductor package using such film
‌
US Patent 7479705 Semiconductor device
‌
US Patent 7485502 Integrated circuit underfill package system
‌
US Patent 7485899 Semiconductor package having an optical device and the method of making the same
‌
US Patent 7489044 Semiconductor package and fabrication method thereof
‌
US Patent 7495325 Optical die-down quad flat non-leaded package
‌
US Patent 7495332 Multilayer printed wiring board
‌
US Patent 7495346 Semiconductor package
‌
US Patent 7498665 Integrated circuit leadless package system
‌
US Patent 7498666 Stacked integrated circuit
‌
US Patent 7498667 Stacked integrated circuit package-in-package system
‌
US Patent 7498672 Micropin heat exchanger
‌
US Patent 7498676 Semiconductor device
‌
US Patent 7501314 Heat sink and method for fabricating the same
‌
US Patent 7501693 LDO regulator with ground connection through package bottom
‌
US Patent 7501697 Integrated circuit package system
‌
US Patent 7501701 Rewiring substrate strip having a plurality of semiconductor component positions
‌
US Patent 7501709 BGA package with wiring schemes having reduced current loop paths to improve cross talk control and characteristic impedance
‌
US Patent 7504733 Semiconductor die package
‌
US Patent 7504735 Manufacturing method of resin-molding type semiconductor device, and wiring board therefor
‌
US Patent 7504736 Semiconductor packaging mold and method of manufacturing semiconductor package using the same
‌
US Patent 7508067 Semiconductor insulation structure
‌
US Patent 7508070 Two dimensional stacking using interposers
‌
US Patent 7508073 Wiring board, semiconductor device using the same, and method for manufacturing wiring board
‌
US Patent 7514299 Chip package structure and manufacturing method thereof
‌
US Patent 7514792 Semiconductor device and manufacturing method thereof
‌
US Patent 11189552 Semiconductor package
‌
US Patent 7517733 Leadframe design for QFN package with top terminal leads
‌
US Patent 7517788 System, apparatus, and method for advanced solder bumping
‌
US Patent 7518211 Chip and package structure
‌
US Patent 7518230 Semiconductor chip and semiconductor device
‌
US Patent 7518252 Thin-film semiconductor substrate, method of manufacturing thin-film semiconductor substrate, method of crystallization, apparatus for crystallization, thin-film semiconductor device, and method of manufacturing thin-film semiconductor device
‌
US Patent 7525191 Semiconductor light source device
‌
US Patent 7525192 Printed circuit board with quartz crystal oscillator
‌
US Patent 7531844 Light emitting element
‌
US Patent 7534715 Methods including fluxless chip attach processes
‌
US Patent 7535111 Semiconductor component with semiconductor chip and adhesive film, and method for its production
‌
US Patent 7535113 Reduced inductance in ball grid array packages
‌
US Patent 7538045 Coating process to enable electrophoretic deposition
‌
US Patent 7538423 Heat sink, electronic device, method of manufacturing heat sink, and method of manufacturing electronic device
‌
US Patent 7538427 Microchannel structure and manufacturing method therefor, light source device, and projector
‌
US Patent 7541221 Integrated circuit package system with leadfinger support
‌
US Patent 7541662 Packaging chip having inductor therein
‌
US Patent 7541668 Package frame and semiconductor package using the same
‌
US Patent 7544598 Semiconductor device and method of manufacturing the same
‌
US Patent 7545035 Semiconductor device having several assembled integrated-circuit chips and method of assembling and electrically connecting the integrated-circuit chips
‌
US Patent 7547972 Laminated structure, very-large-scale integrated circuit wiring board, and method of formation thereof
‌
US Patent 7550319 Low temperature co-fired ceramic (LTCC) tape compositions, light emitting diode (LED) modules, lighting devices and method of forming thereof
‌
US Patent 7550835 Chip stack package utilizing a dummy pattern die between stacked chips for reducing package size
‌
US Patent 7550854 Integrated interconnect arrangement
‌
US Patent 7550857 Stacked redistribution layer (RDL) die assembly package
‌
US Patent 7553764 Silicon wafer having through-wafer vias
‌
US Patent 7554193 Semiconductor device
‌
US Patent 7556984 Package structure of chip and the package method thereof
‌
US Patent 7557432 Thermally enhanced power semiconductor package system
‌
US Patent 7557453 Semiconductor device, method of manufacturing a semiconductor device and substrate to be used to manufacture a semiconductor device
‌
US Patent 7560804 Integrated circuit package and method of making the same
‌
US Patent 7560812 Cooling module against ESD and electronic package, assembly and system using the same
‌
US Patent 7563644 Optical device and method for fabricating the same
‌
US Patent 7563652 Method for encapsulating sensor chips
‌
US Patent 7566962 Semiconductor package structure and method for manufacturing the same
‌
US Patent 7569906 Method for fabricating condenser microphone and condenser microphone
‌
US Patent 7573119 Semiconductor device
‌
US Patent 7576431 Semiconductor chip package and multichip package
‌
US Patent 7576433 Semiconductor memory device and manufacturing method thereof
‌
US Patent 7576437 Printed circuit board of semiconductor package and method for mounting semiconductor package using the same
‌
US Patent 7579217 Methods of making a die-up ball grid array package with printed circuit board attachable heat spreader
‌
US Patent 7586182 Packaged semiconductor die and manufacturing method thereof
‌
US Patent 7586199 Structures, architectures, systems, methods, algorithms and software for configuring and integrated circuit for multiple packaging types
‌
US Patent 7589400 Inverter and vehicle drive unit using the same
‌
US Patent 7589411 Device for electrical connection of an integrated circuit chip
‌
US Patent 7589414 I/O Architecture for integrated circuit package
‌
US Patent 7589419 Side connectors for RFID chip
‌
US Patent 7592701 Electrode structure, part mounting structure and liquid crystal display unit equipped with the part mounting structure
‌
US Patent 7592704 Etched interposer for integrated circuit devices
‌
US Patent 7598610 Plate structure having chip embedded therein and the manufacturing method of the same
‌
US Patent 7598622 Encapsulation of a chip module
‌
US Patent 7602039 Programmable capacitor associated with an input/output pad
‌
US Patent 7605457 Semiconductor device and method of manufacturing the same
‌
US Patent 7605477 Stacked integrated circuit assembly
‌
US Patent 7608863 Submount assembly and method of preparing optical module
‌
US Patent 7615860 Rigid-flex printed circuit board with weakening structure
‌
US Patent 7618844 Method of packaging and interconnection of integrated circuits
‌
US Patent 7622792 Semiconductor device and method of manufacturing the same
‌
US Patent 7626258 Cap wafer, semiconductor chip having the same, and fabrication method thereof
‌
US Patent 7629683 Thermal management of electronic devices
‌
US Patent 7629696 Plastic semiconductor package having improved control of dimensions
‌
US Patent 7633167 Semiconductor device and method for manufacturing same
‌
US Patent 7633168 Method, system, and apparatus for a secure bus on a printed circuit board
‌
US Patent 7642136 Method and apparatus for reducing stresses applied to bonded interconnects between substrates
‌
US Patent 7649255 Determining chip separation by comparing coupling capacitances
‌
US Patent 7651938 Void reduction in indium thermal interface material
‌
US Patent 7652305 Methods and apparatus to improve frit-sealed glass package
‌
US Patent 7652372 Microfluidic cooling of integrated circuits
‌
US Patent 7652375 Semiconductor device and method of manufacturing the same
‌
US Patent 7656022 Wiring board and manufacturing method for wiring board
‌
US Patent 7656030 Semiconductor device
‌
US Patent 7656039 Multi chip module
‌
US Patent 7659615 High power package with dual-sided heat sinking
‌
US Patent 7663204 Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications
‌
US Patent 7666716 Fabrication method of semiconductor package
‌
US Patent 7667284 Method of manufacturing organic electroluminescent device and organic electroluminescent device
‌
US Patent 7667309 Space-efficient package for laterally conducting device
‌
US Patent 7671434 Electronic component, laser device, optical writing device and image forming apparatus
‌
US Patent 7671451 Semiconductor package having double layer leadframe
‌
US Patent 7675131 Flip-chip image sensor packages and methods of fabricating the same
‌
US Patent 7675167 Electronic device package heat sink assembly
‌
US Patent 7679168 Printed circuit board with differential pair arrangement
‌
US Patent 7679169 Stacked integrated circuit leadframe package system
‌
US Patent 7683461 Integrated circuit leadless package system
‌
US Patent 7683468 Enabling uniformity of stacking process through bumpers
‌
US Patent 7683471 Display driver integrated circuit device, film, and module
‌
US Patent 7683495 Integrated circuit package substrate having configurable bond pads
‌
US Patent 7691745 Land patterns for a semiconductor stacking structure and method therefor
‌
US Patent 7692287 Semiconductor device and wiring board
‌
US Patent 7692295 Single package wireless communication device
‌
US Patent 7696626 Semiconductor device and method of arranging pad thereof
‌
US Patent 7701061 Semiconductor device with solder balls having high reliability
‌
US Patent 7701063 Semiconductor device
‌
US Patent 7705446 Package structure having semiconductor chip embedded therein and method for fabricating the same
‌
US Patent 7709935 Reversible leadless package and methods of making and using same
‌
US Patent 7709950 Silicon wafer having through-wafer vias
‌
US Patent 7713790 Method and system of tape automated bonding
‌
US Patent 7714432 Ceramic/organic hybrid substrate
‌
US Patent 7719079 Chip carrier substrate capacitor and method for fabrication thereof
‌
US Patent 7719110 Flip chip package including a non-planar heat spreader and method of making the same
‌
US Patent 7719122 System-in-package packaging for minimizing bond wire contamination and yield loss
‌
US Patent 7723146 Integrated circuit package system with image sensor system
‌
US Patent 7727815 Reactive gettering in phase change solders to inhibit oxidation at contact surfaces
‌
US Patent 7728428 Multilayer printed circuit board
‌
US Patent 7732328 Method of fabricating semiconductor package structure
‌
US Patent 7732934 Semiconductor device having conductive adhesive layer and method of fabricating the same
‌
US Patent 7736930 Optical die-down quad flat non-leaded package
‌
US Patent 7741214 Method of forming a semiconductor device featuring copper wiring layers of different widths having metal capping layers of different thicknesses formed thereon
‌
US Patent 7741726 Integrated circuit underfill package system
‌
US Patent 7745322 Wire bond interconnection
‌
US Patent 7745913 Power semiconductor component with a power semiconductor chip and method for producing the same
‌
US Patent 7755187 Load driving device
‌
US Patent 7759218 Indented lid for encapsulated devices and method of manufacture
‌
US Patent 7759787 Packaging substrate having pattern-matched metal layers
‌
US Patent 7759795 Printed circuit board having reliable bump interconnection structure, method of fabricating the same, and semiconductor package using the same
‌
US Patent 7763983 Stackable microelectronic device carriers, stacked device carriers and methods of making the same
‌
US Patent 7767496 Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
‌
US Patent 7767497 Microelectronic package element and method of fabricating thereof
‌
US Patent 7768139 Power semiconductor module
‌
US Patent RE41510 Lead frame
‌
US Patent 7777352 Semiconductor device with semiconductor device components embedded in plastic package compound
‌
US Patent 7781264 Method for fabricating flip-chip semiconductor package with lead frame as chip carrier
‌
US Patent 7781323 Semiconductor device and manufacturing method thereof
‌
US Patent 7781332 Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer
‌
US Patent 7786555 Semiconductor devices with multiple heat sinks
‌
US Patent 7786582 System for providing a redistribution metal layer in an integrated circuit
‌
US Patent 7786594 Wafer level stack structure for system-in-package and method thereof
‌
US Patent 7786595 Stacked chip package structure with leadframe having bus bar
‌
US Patent 7786605 Stacked semiconductor components with through wire interconnects (TWI)
‌
US Patent 7790598 System, apparatus, and method for advanced solder bumping
‌
US Patent 7791173 Chip having side pad, method of fabricating the same and package using the same
‌
US Patent 7791188 Heat spreader having single layer of diamond particles and associated methods
‌
US Patent 7795732 Ceramic wiring board and process for producing the same, and semiconductor device using the same
‌
US Patent 7800206 Semiconductor device
‌
US Patent 7800207 Method for connecting a die attach pad to a lead frame and product thereof
‌
US Patent 7808097 Low temperature co-fired ceramic (LTCC) tape compositions, light-emitting diode (LED) modules, lighting devices and methods of forming thereof
‌
US Patent 7808101 3D smart power module
‌
US Patent 7812428 Secure connector grid array package
‌
US Patent 7816249 Method for producing a semiconductor device using a solder alloy
‌
US Patent 7816690 Light-emitting device
‌
US Patent 7816769 Stackable packages for three-dimensional packaging of semiconductor dice
‌
US Patent 7816771 Stacked chip package structure with leadframe having inner leads with transfer pad
‌
US Patent 7816782 Wiring substrate for mounting semiconductors, method of manufacturing the same, and semiconductor package
‌
US Patent 7816791 Bonding pad for contacting a device
‌
US Patent 7821111 Semiconductor device having grooved leads to confine solder wicking
‌
US Patent 7821132 Contact pad and method of forming a contact pad for an integrated circuit
‌
US Patent 7821140 Semiconductor device and wire bonding method
‌
US Patent 7825504 Semiconductor package and multi-chip semiconductor package using the same
‌
US Patent 7825520 Stacked redistribution layer (RDL) die assembly package
‌
US Patent 7830017 Wafer level chip scale package, method of manufacturing the same, and semiconductor chip module including the wafer level chip scale package
‌
US Patent 7834429 Lead frame and method of manufacturing the same and semiconductor device
‌
US Patent 7834441 Multilayer substrate and method of manufacturing the same
‌
US Patent 7834461 Semiconductor apparatus
‌
US Patent 7834462 Electric device, stack of electric devices, and method of manufacturing a stack of electric devices
‌
US Patent 7834467 Layer between interfaces of different components in semiconductor devices
‌
US Patent 7838899 Integrated circuit package system with image sensor system
‌
US Patent 7847397 Nanoparticles with covalently bonded stabilizer
‌
US Patent 7847399 Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles
‌
US Patent 7847419 Semiconductor package with pad parts electrically connected to bonding pads through re-distribution layers
‌
US Patent 7851811 Stackable optoelectronics chip-to-chip interconnects and method of manufacturing
‌
US Patent 7851816 Stackable optoelectronics chip-to-chip interconnects and method of manufacturing
‌
US Patent 7851904 Semiconductor device, method for manufacturing the same, and semiconductor device mounting structure
‌
US Patent 7851905 Microelectronic package and method of cooling an interconnect feature in same
‌
US Patent 7851909 Group III nitride based flip-chip integrated circuit and method for fabricating
‌
US Patent 7855102 Method, system, and apparatus for a secure bus on a printed circuit board
‌
US Patent 7855449 Cooling device for a light-emitting semiconductor device and a method of manufacturing such a cooling device
‌
US Patent 7855463 Method for producing a circuit module comprising at least one integrated circuit
‌
US Patent 7859089 Copper straps
‌
US Patent 7859101 Die-up ball grid array package with die-attached heat spreader
‌
US Patent 7863734 Dual-sided chip attached modules
‌
US Patent 7863761 Integrated circuit package system with molding vents
‌
US Patent 7863762 Method of packaging and interconnection of integrated circuits
‌
US Patent 7867819 Semiconductor package including flip chip controller at bottom of die stack
‌
US Patent 7868468 Wire bonding structure and method that eliminates special wire bondable finish and reduces bonding pitch on substrates
‌
US Patent 7868469 Adapter board and method for manufacturing same, probe card, method for inspecting semiconductor wafer, and method for manufacturing semiconductor device
‌
US Patent 7868470 Semiconductor chip package and multichip package
‌
US Patent 7871833 Determining chip separation by comparing coupling capacitances
‌
US Patent 7872335 Lead frame-BGA package with enhanced thermal performance and I/O counts
‌
US Patent 7872352 Carbon nanotube bond pad structure and method therefor
‌
US Patent 7875964 Multi-chip semiconductor connector and method
‌
US Patent 7875969 Rigid-flex printed circuit board with weakening structure
‌
US Patent 7879656 Multilayer substrate and method of manufacturing the same
‌
US Patent 7880291 Integrated circuit package and integrated circuit module
‌
US Patent 7880310 Direct device attachment on dual-mode wirebond die
‌
US Patent 7884482 Flip-chip mounting substrate
‌
US Patent 7888791 Device for electrical connection of an integrated circuit chip
‌
US Patent 7892973 Method for manufacturing a semiconductor device
‌
US Patent 7893540 Semiconductor memory device and manufacturing method thereof
‌
US Patent 7893546 Ball grid array package enhanced with a thermal and electrical connector
‌
US Patent 7901998 Packaging substrate having pattern-matched metal layers
‌
US Patent 7906424 Conductor bump method and apparatus
‌
US Patent 7906852 Semiconductor device and manufacturing method of the same
‌
US Patent 7911039 Component arrangement comprising a carrier
‌
US Patent 7915716 Integrated circuit package system with leadframe array
‌
US Patent 7915724 Integrated circuit packaging system with base structure device
‌
US Patent 7923852 Semiconductor package structure with protection bar
‌
US Patent 7928557 Stacked package and method for manufacturing the package
‌
US Patent 7932607 Composite conductive film and semiconductor package using such film
‌
US Patent 7939934 Microelectronic packages and methods therefor
‌
US Patent 7939942 Semiconductor devices and methods of manufacturing thereof
‌
US Patent 7939947 Semiconductor package structure
‌
US Patent 7939950 Chip package structure
‌
US Patent 7943435 Underfill film having thermally conductive sheet
‌
US Patent 7944047 Method and structure of expanding, upgrading, or fixing multi-chip package
‌
US Patent 7944048 Chip scale package for power devices and method for making the same
‌
US Patent 7944061 Semiconductor device having through contacts through a plastic housing composition and method for the production thereof
‌
US Patent 7948066 Integrated circuit package system with lead locking structure
‌
US Patent 7948076 Semiconductor chip assembly with post/base heat spreader and vertical signal routing
‌
US Patent 7948093 Memory IC package assembly having stair step metal layer and apertures
‌
US Patent 7948095 Semiconductor package and method of making the same
‌
US Patent 7951650 Thermal management of electronic devices
‌
US Patent 7952197 Electrical component
‌
US Patent 7955973 Method and apparatus for improvements in chip manufacture and design
‌
US Patent 7956355 Method of manufacturing organic electroluminescent device and organic electroluminescent device
‌
US Patent 7956474 Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types
‌
US Patent 7960815 Leadframe design for QFN package with top terminal leads
‌
US Patent 7964492 Semiconductor device and automotive AC generator
‌
US Patent 7964956 Circuit packaging and connectivity
‌
US Patent 7972903 Semiconductor device having wiring line and manufacturing method thereof
‌
US Patent 7973416 Thru silicon enabled die stacking scheme
‌
US Patent 7977775 Semiconductor device and manufacturing method of the same
‌
US Patent 7977790 Semiconductor device and method of manufacturing the same
‌
US Patent 7977798 Integrated circuit having a semiconductor substrate with a barrier layer
‌
US Patent 7986046 Semiconductor module and method of producing the same
‌
US Patent 7986047 Wire bond interconnection
‌
US Patent 7986048 Package-on-package system with through vias and method of manufacture thereof
‌
US Patent 7989959 Method of forming stacked-die integrated circuit
‌
US Patent 7989960 Semiconductor device
‌
US Patent 7993982 Quad flat non-leaded package and manufacturing method thereof
‌
US Patent 7994615 Direct contact leadless package for high current devices
‌
US Patent 7999341 Display driver integrated circuit device, film, and module
‌
US Patent 7999394 Void reduction in indium thermal interface material
‌
US Patent 8003536 Electromigration resistant aluminum-based metal interconnect structure
‌
US Patent 8004080 Edge mounted integrated circuits with heat sink
‌
US Patent 8004095 Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
‌
US Patent 8008765 Semiconductor package having adhesive layer and method of manufacturing the same
‌
US Patent 8008773 Semiconductor device and method for fabricating semiconductor device
‌
US Patent 8008787 Integrated circuit package system with delamination prevention structure
‌
US Patent 8012776 Methods of manufacturing imaging device packages
Edits on 13 Dec, 2021
Golden AI profile picture
Golden AI
edited on 13 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8012776 Methods of manufacturing imaging device packages
Edits on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8008765 Semiconductor package having adhesive layer and method of manufacturing the same
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8008787 Integrated circuit package system with delamination prevention structure
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8008773 Semiconductor device and method for fabricating semiconductor device
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8004080 Edge mounted integrated circuits with heat sink
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 8003536 Electromigration resistant aluminum-based metal interconnect structure
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7999394 Void reduction in indium thermal interface material
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7999341 Display driver integrated circuit device, film, and module
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7994615 Direct contact leadless package for high current devices
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7993982 Quad flat non-leaded package and manufacturing method thereof
Edits on 8 Dec, 2021
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7989959 Method of forming stacked-die integrated circuit
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7989960 Semiconductor device
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7986046 Semiconductor module and method of producing the same
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7986047 Wire bond interconnection
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7986048 Package-on-package system with through vias and method of manufacture thereof
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7977790 Semiconductor device and method of manufacturing the same
Golden AI profile picture
Golden AI
edited on 8 Dec, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7977798 Integrated circuit having a semiconductor substrate with a barrier layer

Find more people like Nitin Parekh

Use the Golden Query Tool to discover related individuals, professionals, or experts with similar interests, expertise, or connections in the Knowledge Graph.
Open Query Tool
Access by API
Golden Query Tool
Golden logo
By using this site, you agree to our Terms of Service.