US Patent 7411285 Low profile stacked semiconductor chip package

A stacked semiconductor chip package comprising a first semiconductor chip having an upper surface, a lower surface opposed to said upper surface, and a plurality of conductive metal lines formed on said upper surface of said first semiconductor chip; a plurality of metal elements each having a first arm portion located on said upper surface of said first semiconductor chip and connected electrically to a corresponding one of said metal lines, a second arm portion located on said lower surface of said first semiconductor chip; and a second semiconductor chip having a lower surface and a plurality of conductive bumps provided on said lower surface, and mounted on said upper surface of said first semiconductor chip in such a manner that said solder bumps of said second semiconductor chip is electrically connected to said corresponding conductive metal lines on said upper surface of said first semiconductor chip.