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Khanh Dang
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Edits on 25 Sep, 2022
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Lev Kolpakov
edited on 25 Sep, 2022
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https://twitter.com/dangitzkhanh
Edits on 16 Aug, 2022
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Golden AI
edited on 16 Aug, 2022
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Founder of
CAP
Edits on 16 Aug, 2022
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Golden AI
edited on 16 Aug, 2022
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Founder of
CAP
Edits on 14 Dec, 2021
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Golden AI
edited on 14 Dec, 2021
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Patent primary examiner of
US Patent 7093052 Bus sampling on one edge of a clock signal and driving on another edge
US Patent 7093057 Display apparatus and method
US Patent 7096285 Network device interface for digitally interfacing data channels to a controller via a network
US Patent 7096298 Reduced cardbus controller
US Patent 7099965 Network device interface for digitally interfacing data channels to a controller a via network
US Patent 7099975 Method of resource arbitration
US Patent 7107372 Communication system and device
US Patent 7107373 Method of hot switching data transfer rate on bus
US Patent 7107379 Method for connecting an expansion module to a programmable electric switching device
US Patent 7107380 Configuration for dockable portable computers using a single ethernet physical layer chip and transformer
US Patent 7111099 Information handling system with improved bus system
US Patent 7114019 System and method for data transmission
US Patent 7114021 System and method providing configuration services for communications devices
US Patent 7117277 Flexibility of design of a bus interconnect block for a data processing apparatus
US Patent 7117279 Keycode page switching apparatus and method for the same
US Patent 7117283 Multi-master extended I2C protocol
US Patent 7120719 Electronic apparatus
US Patent 7124208 Method and apparatus for enumerating devices on a link
US Patent 7124225 Method and apparatus for multi-interrupt controller for reducing hardware interrupts to DSP
US Patent 7124231 Split transaction reordering circuit
US Patent 7127532 Data communication apparatus and transmission reservation managing method
US Patent 7133937 Input devices for entering data into an electronic medical record (EMR)
US Patent 7133955 System and method for selecting fabric master
US Patent 7136944 Method and apparatus for using address traps to pace writes to peripheral devices
US Patent 7136956 Semiconductor device
US Patent 7139854 Pipelining access to serialization tokens on a bus
US Patent 7139855 High performance synchronization of resource allocation in a logically-partitioned system
US Patent 7143200 Semiconductor integrated circuit
US Patent 7149829 Various methods and apparatuses for arbitration among blocks of functionality
US Patent 7149831 Batch processing of interrupts
US Patent 7155552 Apparatus and method for highly available module insertion
US Patent 7155557 Communication mechanism
US Patent 7167935 Accessory control interface
US Patent 7171496 Data bus width conversion apparatus and data processing apparatus
US Patent 7171502 USB system having card-type USB interface connector
US Patent 7174401 Look ahead split release for a data bus
US Patent 7174406 System and method for arbitrating access to a shared resource
US Patent 7174407 Extendable computer system
US Patent 7181549 Semiconductor integrated circuit
US Patent 7185121 Method of accessing memory via multiple slave ports
US Patent 7185123 Method and apparatus for allocating bandwidth on a transmit channel of a bus
US Patent 7185132 USB controller with intelligent transmission mode switching function and the operating method thereof
US Patent 7188205 Mapping of hot-swap states to plug-in unit states
US Patent 7191274 Method and system for providing independent server functionality in a single personal computer
US Patent 7200693 Memory system and method having unidirectional data buses
US Patent 7200699 Scalable, two-stage round robin arbiter with re-circulation and bounded latency
US Patent 7203785 Apparatus and method for parallel and serial PCI hot plug signals
US Patent 7206845 Method, system and program product for monitoring and controlling access to a computer system resource
US Patent 7206867 Method and apparatus for robust addressing on a dynamically configurable bus
US Patent 7206875 Expander device capable of persistent reservations and persistent affiliations
US Patent 7206878 Voltage level bus protocol for transferring data
US Patent 7206978 Error detection in a circuit module
US Patent 7209993 Apparatus and method for interrupt control
US Patent 7213094 Method and apparatus for managing buffers in PCI bridges
US Patent 7219175 Method and system for improving the latency in a data transmission system
US Patent 7219180 Combined uninterruptable power supply and bus control module to improve power management and legacy support
US Patent 7222200 Method for synchronizing processors in SMI following a memory hot plug event
US Patent 7222201 Virtual endpoint for USB devices
US Patent 7222313 Creating description files used to configure components in a distributed system
US Patent 7225285 Assigning interrupts in multi-master systems
US Patent 7228364 System and method of SCSI and SAS hardware validation
US Patent 7228371 Computer workstation automated analysis system and upgrade determination tool
US Patent 7231467 Method and apparatus for providing an inter integrated circuit interface with an expanded address range and efficient priority-based data throughput
US Patent 7231477 Bus controller
US Patent 7231484 Method and memory controller for scalable multi-channel memory access
US Patent 7231485 Universal serial bus (USB) interface for mass storage device
US Patent 7234017 Computer system architecture for a processor connected to a high speed bus transceiver
US Patent 7237053 Clock switching circuit for a hot plug
US Patent 7243181 Signal bus arrangement
US Patent 7246181 Device and method for identifying a communication interface that performs an operating parameter closer to a desired performance level than another communication interface performs the operating parameter
US Patent 7246184 Method for configuring and/or operating an automation device
US Patent 7246192 Serial/parallel ATA controller and converter
US Patent 7251703 Method of time stamping to enable device bridging over dissimilar buses
US Patent 7254657 Dual mode capability for system bus
US Patent 7257657 Method and apparatus for counting instruction execution and data accesses for specific types of instructions
US Patent 7257658 Message based interrupt table
US Patent 7260661 Processing replies to request packets in an advanced switching context
US Patent 7260664 Interrupt mechanism on an IO adapter that supports virtualization
US Patent 7263567 Method and apparatus for lowering the die temperature of a microprocessor and maintaining the temperature below the die burn out
US Patent 7266626 Method and apparatus for connecting an additional processor to a bus with symmetric arbitration
US Patent 7269673 Cable with circuitry for asserting stored cable data or other information to an external device or user
US Patent 7269676 Method and apparatus for controlling an external RF device with a dual processor system
US Patent 7272669 Providing compatibility with both electrically isolated and non-isolated modules in an ethernet system
US Patent 7275121 System and method for hardware assisted resource sharing
US Patent 7277970 Network device interface for digitally interfacing data channels to a controller via a network
US Patent 7277976 Multilayer system and clock control method
US Patent 7281065 Long latency interface protocol
US Patent 7284078 Deterministic field bus and process for managing same such that when transmissions from one subscriber station are enabled transmissions from other subscriber stations are disabled
US Patent 7284079 Method and apparatus for constructing wired-and bus systems
US Patent 7284083 Dynamically configuring resources for cycle translation in a computer system
US Patent 7287112 Dynamic reconfiguration interrupt system and method
US Patent 7287113 Method of and apparatus for controlling bidirectional streams of isochronous data flowing between an application and a bus structure
US Patent 7290073 Master slave serial bus apparatus
US Patent 7293126 Enhanced structure of extensible time-sharing bus capable of reducing pin number, extending memory capacity, and performing I/O mapping access and block access
US Patent 7296096 Method and system for configuring an interconnect device
US Patent 7296104 Automated calibration of I/O over a multi-variable eye window
US Patent 7296105 Method and apparatus for configuring an interconnect to implement arbitration
US Patent 7299312 Telecommunication apparatus
US Patent 7308514 Configuring a communication link interface
US Patent 7313643 PCI-express to PCI/PCI X translator
US Patent 7320045 Automatic detection of the bit width of a data bus
US Patent 7321947 Systems and methods for managing multiple hot plug operations
US Patent 7325649 Loudspeaker with progressively damped acoustical chamber
US Patent 7340548 On-chip bus
US Patent 7340550 USB schedule prefetcher for low power
US Patent 7343434 Buffer management within SLS (simple load store) apertures for inter-endpoint communication in advanced switching fabric
US Patent 7343437 Synchronization method and control system for the time synchronization of slave units and a synchronizable slave unit
US Patent 7343440 Integrated circuit with a scalable high-bandwidth architecture
US Patent 7346725 Method and apparatus for generating traffic in an electronic bridge via a local controller
US Patent 7349998 Bus control system for integrated circuit device with improved bus access efficiency
US Patent 7353317 Method and apparatus for implementing heterogeneous interconnects
US Patent 7359995 Peripheral device connection current compensation circuit
US Patent 7370129 Retry strategies for use in a streaming environment
US Patent 7370133 Storage controller and methods for using the same
US Patent 7376771 Generic interface for operating modes of modules
US Patent 7376776 Motherboard assembly
US Patent 7380039 Apparatus, method and system for aggregrating computing resources
US Patent 7383369 Managing a resource lock
US Patent 7386640 Method, apparatus and system to generate an interrupt by monitoring an external interface
US Patent 7389373 Asynchronous arbitration device and microcontroller comprising such an arbitration device
US Patent 7389374 High latency interface between hardware components
US Patent 7398339 Method and system for improving the latency in a data transmission system
US Patent 7406544 Semiconductor integrated circuit
US Patent 7409481 Data processing system, method and interconnect fabric supporting destination data tagging
US Patent 7409484 Integrated circuit having reduced pin count
US Patent 7415553 Automatic cluster join protocol
US Patent 7415555 Bus bridge device
US Patent 7415562 Variable-function or multi-function apparatus and methods
US Patent 7421521 System, method and device for real time control of processor
US Patent 7421527 Transmission apparatus and transmission method
US Patent 7421531 Isolating system that couples fieldbus data to a network
US Patent 7424569 Data transfer control device and electronic equipment
US Patent 7426587 Semiconductor integrated circuit
US Patent 7426596 Integrated circuit with a scalable high-bandwidth architecture
US Patent 7426599 Systems and methods for writing data with a FIFO interface
US Patent 7426600 Bus switch circuit and bus switch system
US Patent 7428601 Semiconductor integrated circuit
US Patent 7430618 Data transfer control device and electronic equipment
US Patent 7433984 Time-based weighted round robin arbiter
US Patent 7433987 Computer apparatus for interconnecting an industry standard computer to a proprietary backplane and its associated peripherals
US Patent 7437495 Method and apparatus for assigning bus grant requests
US Patent 7441059 Method and device for data communication
US Patent 7441063 KVM system for controlling computers and method thereof
US Patent 7444449 Method, computer program product and computer system for controlling execution of an interruption routine
US Patent 7444451 Adaptive interrupts coalescing system with recognizing minimum delay packets
US Patent 7444454 Systems and methods for interconnection of multiple FPGA devices
US Patent 7444455 Integrated gigabit ethernet PCI-X controller
US Patent 7451244 Multi-protocol bus device
US Patent 7451260 Interleave mechanism for a computing environment
US Patent 7454551 Reconstructing transaction order using clump tags
US Patent 7457901 Microprocessor apparatus and method for enabling variable width data transfers
US Patent 7457904 Methods and systems for a reference clock
US Patent 7457905 Method for request transaction ordering in OCP bus to AXI bus bridge design
US Patent 7464209 Controlling resource transfers using locks in a logically partitioned computer system
US Patent 7467246 Secure local network
US Patent 7467252 Configurable I/O bus architecture
US Patent 7469308 Hierarchical bus structure and memory access protocol for multiprocessor systems
US Patent 7472213 Resource management device
US Patent 7475164 Apparatus, system, and method for automated device configuration and testing
US Patent 7475168 Various methods and apparatus for width and burst conversion
US Patent 7478140 System and method for sending electronic mail and parcel delivery notification using recipient's identification information
US Patent 7478185 Directly initiating by external adapters the setting of interruption initiatives
US Patent 7478186 Interrupt coalescer for DMA channel
US Patent 7478191 Method for automatically switching USB peripherals between USB hosts
US Patent 7484024 Apparatus and method for interrupt source signal allocation
US Patent 7484027 Apparatus and method for configurable device pins
US Patent 7484028 Burst-capable bus bridges for coupling devices to interface buses
US Patent 7484030 Storage controller and methods for using the same
US Patent 7487266 Communication system and method, and distributed control system and method
US Patent 7487268 Long latency interface protocol
US Patent 7487277 Apparatus, system, and method for overriding resource controller lock ownership
US Patent 7487279 Achieving both locking fairness and locking performance with spin locks
US Patent 7490176 Serial attached SCSI backplane and detection system thereof
US Patent 7493434 Determining the value of internal signals in a malfunctioning integrated circuit
US Patent 7493436 Interrupt handling using simultaneous multi-threading
US Patent 7493439 Systems and methods for providing performance monitoring in a memory system
US Patent 7500031 Ring-based cache coherent bus
US Patent 7500032 Cable with circuitry for asserting stored cable data or other information to an external device or user
US Patent 7500033 Universal serial bus transmitter
US Patent 7500040 Method for synchronizing processors following a memory hot plug event
US Patent 7500042 Access control device for bus bridge circuit and method for controlling the same
US Patent 7500043 Array of data processing elements with variable precision interconnect
US Patent 7500047 System and method for processing commands
US Patent 7502880 Apparatus and method for quad-pumped address bus
US Patent 7502882 Advanced mezzanine card adapter
US Patent 7506087 Method for configuring a Peripheral Component Interconnect Express (PCIE)
US Patent 7506093 Apparatus and method for converting parallel and serial PCI hot plug signals
US Patent 7509449 Internet SCSI communication via UNDI services
US Patent 7512724 Multi-thread peripheral processing using dedicated peripheral bus
US Patent 7519750 Linear burst mode synchronizer for passive optical networks
US Patent 7519753 Communication system
US Patent 7523237 Method and protocol for diagnostics or arbitrarily complex networks of devices
US Patent 7523238 Device and method to reduce simultaneous switching noise
US Patent 7529875 Assigning interrupts for input/output (I/O) devices among nodes of a non-uniform memory access (NUMA) system
US Patent 7539784 Hard disk type detecting circuit and hard disk connecting port having the hard disk type detecting circuit
US Patent 7543088 Various methods and apparatuses for width and burst conversion
US Patent 7543090 Double-pumped/quad-pumped variation mechanism for source synchronous strobe lockout
US Patent 7543101 System of accessing data in a graphics system and method thereof
US Patent 7549004 Split filtering in multilayer systems
US Patent 7549006 Structure of object stacks for driver
US Patent 7552253 Systems and methods for determining size of a device buffer
US Patent 7552256 Network device interface for digitally interfacing data channels to a controller via a network
US Patent 7552270 Signal transmission method, bridge unit, and information processing apparatus
US Patent 7555585 Optimized performance and power access to a shared resource in a multiclock frequency system on a chip application
US Patent 7555589 Multi-protocol serial interface system
US Patent 7558898 Port replicating apparatus
US Patent 7562171 Method for interfacing components of a computing system with a pair of unidirectional, point-to-point buses
US Patent 7562175 Internet SCSI communication via UNDI services
US Patent 7565471 Message signaled interrupt extended (MSI-X) auto clear and failsafe lock
US Patent 7565473 Semiconductor integrated circuit and electronic equipment
US Patent 7568059 Low-power reconfigurable architecture for simultaneous implementation of distinct communication standards
US Patent 7568060 Method and system for interfacing components of a computing system with a pair of unidirectional, point-to-point buses
US Patent 7571271 Lane merging
US Patent 7571273 Bus/device/function translation within and routing of communications packets in a PCI switched-fabric in a multi-host environment utilizing multiple root switches
US Patent 7577780 Fine-grained bandwidth control arbiter and the method thereof
US Patent 7581054 Data processing system
US Patent 7584318 Apparatus for coordinating interoperability between devices of varying capabilities in a network
US Patent 7590769 Data communication apparatus and transmission reservation managing method
US Patent 7590790 Bus device
US Patent 7594053 Adaptive object level locking
US Patent 7596649 Motherboard
US Patent 7596653 Technique for broadcasting messages on a point-to-point interconnect
US Patent 7600064 System and method for provisioning a remote library for an electronic device
US Patent 7600066 Methods for identifying bridge devices and systems thereof
US Patent 7600067 Methods for identifying bridge devices and systems thereof
US Patent 7600068 Programmable control interface device
US Patent 7603491 Bandwidth conserving protocol for command-response bus system
US Patent 7603503 Efficiency based arbiter
US Patent 7606955 Single wire bus for connecting devices and methods of operating the same
US Patent 7613849 Integrated circuit and method for transaction abortion
US Patent 7620760 Non-high impedence device and method for reducing energy consumption
US Patent 7624213 Passing identification information
US Patent 7624219 Bus node
US Patent 7634602 Bus system with few control lines
US Patent 7634604 Systems for generating synchronized events and images
US Patent 7634610 Reconstructing transaction order using clump tags
US Patent 7640387 Method and apparatus for implementing heterogeneous interconnects
US Patent 7644219 System and method for managing the sharing of PCI devices across multiple host operating systems
US Patent 7664890 System control device
US Patent 7664901 Data processing apparatus and method for arbitrating access to a shared resource
US Patent 7668977 Method for exchanging information between devices connected via a communication link
US Patent 7668997 High speed bus system that incorporates uni-directional point-to-point buses
US Patent 7668998 Methods, systems, and devices for providing an interrupt scheme in automated pharmaceutical dispensing machines without centralized arbitration
US Patent 7668999 Computer system with improved bus handling
US Patent 7676618 Controlling resource transfers in a logically partitioned computer system
US Patent 7685352 System and method for loose ordering write completion for PCI express
US Patent 7689728 Method and apparatus for describing ACPI machine language in computer having multibridge PCI structure, and program thereof
US Patent 7694056 Variable-function or multi-function apparatus and methods
US Patent 7702836 Parallel processing device and exclusive control method
US Patent 7711873 Bandwidth control and power saving by interface aggregation
US Patent 7716386 Component identification and transmission system
US Patent 7716405 Computer system
US Patent 7721034 System and method for managing system management interrupts in a multiprocessor computer system
US Patent 7725637 Methods and apparatus for generating system management interrupts
US Patent 7730227 Memory mapped I/O bus selection
US Patent 7730247 Information processing apparatus
US Patent 7730248 Interrupt morphing and configuration, circuits, systems and processes
US Patent 7734854 Device, system, and method of handling transactions
US Patent 7739437 Access arbiter and arbitrable condition verification device
US Patent 7743191 On-chip shared memory based device architecture
US Patent 7743199 Method and apparatus for obtaining trace information of multiple processors on an SoC using a segmented trace ring bus to enable a flexible trace output configuration
US Patent 7747801 Reducing information reception delays
US Patent 7752346 Universal routing in PCI-Express fabrics
US Patent 7752353 Signaling an interrupt request through daisy chained devices
US Patent 7752357 High-definition multimedia interface receiver/transmitter chipset
US Patent 7752365 Bi-directional single conductor interrupt line for communication bus
US Patent 7752370 Splitting one hardware interrupt to multiple handlers
US Patent 7752371 System and method for interrupt abstraction
US Patent 7752373 System and method for controlling memory operations
US Patent 7752376 Flexible configuration space
US Patent 7757021 Slave bus subscriber for a serial data bus
US Patent 7757028 Multi-priority messaging
US Patent 7761631 Data processing system, method and interconnect fabric supporting destination data tagging
US Patent 7779187 Data communication circuit and arbitration method
US Patent 7779189 Method, system, and computer program product for pipeline arbitration
US Patent 7783807 Controlling resource transfers in a logically partitioned computer system
US Patent 7783810 Apparatus and method of processing information
US Patent 7783815 High latency interface between hardware components
US Patent 7783822 Systems and methods for improving performance of a routable fabric
US Patent 7788431 Dynamic I2C slave device address decoder
US Patent 7793028 Long latency interface protocol
US Patent 7805556 Interrupt control apparatus, bus bridge, bus switch, image processing apparatus, and interrupt control method
US Patent 7814250 Serialization of data for multi-chip bus implementation
US Patent 7814257 Data transfer apparatus and data transfer method
US Patent 7836238 Hot-plug/remove of a new component in a running PCIe fabric
US Patent 7840721 Devices with multiple functions, and methods for switching functions thereof
US Patent 7849239 Interface device
US Patent 7865652 Power control by a multi-port bridge device
US Patent 7873761 Data pipeline management system and method for using the system
US Patent 7877521 Processing apparatus and method of modifying system configuration
US Patent 7882282 Controlling passthrough of communications between multiple buses
US Patent 7882294 On-chip bus
US Patent 7886103 Input-output module, processing platform and method for extending a memory interface for input-output operations
US Patent 7886104 Detachable adapter and portable system
US Patent 7886106 USB sharing switch with automatic switching capabilities
US Patent 7886178 Semiconductor memory apparatus
US Patent 7895382 Method and apparatus for qualifying collection of performance monitoring events by types of interrupt when interrupt occurs
US Patent 7899967 Systems for accessing memory card and methods for accessing memory card by a control unit
US Patent 7904626 Arbiter and arbitration method of multiple data accesses
US Patent 7904628 Smart docking system
US Patent 7912993 Methods and media for managing interruption of the out of box experience
US Patent 7917684 Bus translator
US Patent 7921236 Method and apparatus for simultaneous bidirectional signaling in a bus topology
US Patent 7925805 Critical resource management
US Patent 7930460 Universal measurement or protective device
US Patent 7934035 Apparatus, method and system for aggregating computing resources
US Patent 7934036 Interrupt-related circuits, systems, and processes
US Patent 7934046 Access table lookup for bus bridge
US Patent 7937520 General purpose interface controller of resoure limited system
US Patent 7953913 Peripheral device locking mechanism
US Patent 7953914 Clearing interrupts raised while performing operating system critical tasks
US Patent 7958283 Observing an internal link via a second link
US Patent 7958294 Integrated circuit having data transceivers and method of positioning circuits on an integrated circuit
US Patent 7962661 System and method for determining a bus address for a controller within a network
US Patent 7966432 Data processing device adaptable to variable external memory size and endianess
US Patent 7966440 Image processing controller and image forming apparatus
US Patent 7971088 Clock skew controller and integrated circuit including the same
US Patent 7984206 System for debugging throughput deficiency in an architecture using on-chip throughput computations
US Patent 7996593 Interrupt handling using simultaneous multi-threading
US Patent 8001287 Dynamically updating alias location codes with correct location codes during concurrent installation of a component in a computer system
US Patent 8010714 Method for assigning addresses to nodes of a bus system, and installation
US Patent 8010730 Bus converter, semiconductor device, and noise reduction method of bus converter and semiconductor device
Edits on 8 Dec, 2021
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 8010730 Bus converter, semiconductor device, and noise reduction method of bus converter and semiconductor device
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 8010714 Method for assigning addresses to nodes of a bus system, and installation
Edits on 8 Dec, 2021
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 8001287 Dynamically updating alias location codes with correct location codes during concurrent installation of a component in a computer system
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 7996593 Interrupt handling using simultaneous multi-threading
Golden AI
edited on 8 Dec, 2021
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US Patent 7984206 System for debugging throughput deficiency in an architecture using on-chip throughput computations
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 7971088 Clock skew controller and integrated circuit including the same
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 7966440 Image processing controller and image forming apparatus
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 7966432 Data processing device adaptable to variable external memory size and endianess
Golden AI
edited on 8 Dec, 2021
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Patent primary examiner of
US Patent 7962661 System and method for determining a bus address for a controller within a network
Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
US Patent 7958283 Observing an internal link via a second link
Golden AI
edited on 7 Dec, 2021
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US Patent 7958294 Integrated circuit having data transceivers and method of positioning circuits on an integrated circuit
Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
US Patent 7953914 Clearing interrupts raised while performing operating system critical tasks
Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
US Patent 7953913 Peripheral device locking mechanism
Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
US Patent 7937520 General purpose interface controller of resoure limited system
Edits on 7 Dec, 2021
Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
US Patent 7934036 Interrupt-related circuits, systems, and processes
Golden AI
edited on 7 Dec, 2021
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Patent primary examiner of
US Patent 7934046 Access table lookup for bus bridge
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