SBIR/STTR Award attributes
The technical objectives of the proposal are: 1) perform a comprehensive simulation of ~ 4.0 micron-emitting QCLs with suppressed carrier leakage and reduced built-in voltage for achieving pulsed wall-plug efficiency > 15 %; 2) perform a thermal analysis of ~ 4.0 micron-emitting QCL structures and achieve a design for single-spatial-mode operation at 5 W CW output power and 15 % CW wall-plug efficiency; 3) establish the material-related parameters for ~ 4 micron-emitting QCL structures. QCLs will be designed for virtually suppressing the overall carrier leakage out of their active regions and achieving fast carrier extraction from their active regions. In addition, an approach for significantly reducing the overall voltage will be incorporated into the device design. Novel thermal management approaches will be designed in order to minimize the overall thermal conductance of the packaged device. Prototype plans will be created for devices to developed during Phase II, by conducting thermal simulations on fully packaged QCLs. As part of the Option portion of the proposed effort, based on the design reached during the Base portion, ~ 4 micron-emitting QCL structures will be grown and evaluated under pulsed-operation conditions. The grown material will also be used for extracting material-related parameters, to provide a benchmark for QCL material optimization during Phase II. Successful completion of the proposed program will not only enable the realization, in Phase II, of multiwatt-range, highly efficient and long-term reliable ~ 4.0 micron-emitting QCLs, but also provide a springboard for future QCL development for achieving higher power and efficiency at wavelengths below 4 microns.
