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Fritz Fleming

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Edits on 14 Dec, 2021
"Remove inverse infobox"
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Golden AI
edited on 14 Dec, 2021
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Infobox (-117 properties)
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Patent primary examiner of
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US Patent 7089336 Arbitrating and servicing polychronous data requests in Direct Memory Access
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US Patent 7089337 Controlling device connected to IEEE1394 serial bus
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US Patent 7096257 Automatic assignment of addresses to nodes in a network
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US Patent 7096278 Electronically readable name tags for network communications
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US Patent 7096284 Receiving device connected to IEEE1394 serial bus
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US Patent 7100023 System and method for processing complex computer instructions
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US Patent 7100024 Pipelined microprocessor, apparatus, and method for generating early status flags
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US Patent 7100025 Apparatus and method for performing single-instruction multiple-data instructions
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US Patent 7100027 System and method for reproducing system executions using a replay handler
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US Patent 7103683 Method, apparatus, system, and article of manufacture for processing control data by an offload adapter
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US Patent 7107363 Microprocessor having bandwidth management for computing applications and related method of managing bandwidth allocation
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US Patent 7107368 Systems and methods for printing
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US Patent 7107370 Wireless communication portfolio system and device
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US Patent 7107433 Mechanism for resource allocation in a digital signal processor based on instruction type information and functional priority and method of operation thereof
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US Patent 7107438 Pipelined microprocessor, apparatus, and method for performing early correction of conditional branch instruction mispredictions
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US Patent 7111080 Distributing an electronic signal in a stackable device
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US Patent 7111084 Data storage network with host transparent failover controlled by host bus adapter
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US Patent 7111086 High-speed packet transfer in computer systems with multiple interfaces
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US Patent 7111088 Computer system, management device, and logical device selecting method and program
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US Patent 7111091 Device and method for controlling a stream of data packets
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US Patent 7111093 Ping-pong buffer system having a buffer to store a subset of data from a data source
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US Patent 7111155 Digital signal processor computation core with input operand selection from operand bus for dual operations
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US Patent 7114010 Multi-mode controller
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US Patent 7114014 Method and system for data movement in data storage systems employing parcel-based data mapping
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US Patent 7114017 Programmable peripheral switch
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US Patent 7114059 System and method to bypass execution of instructions involving unreliable data during speculative execution
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US Patent 7117278 Method for merging a plurality of data streams into a single data stream
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US Patent 7120679 Configuration of headless devices using configuration service
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US Patent 7120708 Readdressable virtual DMA control and status registers
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US Patent 7120783 System and method for reading and writing a thread state in a multithreaded central processing unit
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US Patent 7124211 System and method for explicit communication of messages between processes running on different nodes in a clustered multiprocessor system
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US Patent 7124214 Method and related apparatus for controlling a peripheral device to transfer data to a bus
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US Patent 7127529 Smart card system having asynchronous communication with the smart card operating either as master or slave
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US Patent 7127534 Read/write command buffer pool resource management using read-path prediction of future resources
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US Patent 7130926 Control plane failure recovery in a network
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US Patent 7130928 Method and apparatus for managing i/o paths on a storage network
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US Patent 7130937 Method for providing a video data streaming service
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US Patent 7133906 System and method for remotely configuring testing laboratories
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US Patent 7134002 Apparatus and method for switching threads in multi-threading processors
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US Patent 7134005 Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte
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US Patent 7134094 Automatic assigning of shortcut keys
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US Patent 7136939 Storage device and method of setting configuration information of same
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US Patent 7136940 Internet refrigerator with web pad and method for operating the same
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US Patent 7136943 Method and apparatus for managing context switches using a context switch history table
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US Patent 7139817 Managing configuration information for multiple devices
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US Patent 7139845 Fibre channel fabric snapshot service
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US Patent 7139851 Method and apparatus for re-synchronizing mirroring pair with data consistency
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US Patent 7143198 Docking station for portable computer
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US Patent 7143203 Storage device control responsive to operational characteristics of a system
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US Patent 7143209 Storage control apparatus and control method thereof
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US Patent 7143267 Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register of a multithreading processor
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US Patent 7143269 Apparatus and method for killing an instruction after loading the instruction into an instruction queue in a pipelined microprocessor
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US Patent 7146438 Device and method for controlling packet flow
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US Patent 7146439 Management of background copy task for point-in-time copies
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US Patent 7146445 Daughtercard-based system software and hardware functionality-defining mechanism
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US Patent 7146486 SIMD processor with scalar arithmetic logic units
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US Patent 7149793 Communication network and method therein
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US Patent 7149818 Method to communicate PHY mean square error to upper layer device driver for rate negotiation
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US Patent 7149822 Information storage device having internal defragmentation capability
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US Patent 7149877 Byte execution unit for carrying out byte instructions in a processor
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US Patent 7149879 Processor and method of automatic instruction mode switching between n-bit and 2n-bit instructions by using parity check
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US Patent 7152154 Apparatus and method for invalidation of redundant branch target address cache entries
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US Patent 7155543 Method for transferring variable isochronous data and apparatus therefor
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US Patent 7155600 Method and logical apparatus for switching between single-threaded and multi-threaded execution states in a simultaneous multi-threaded (SMT) processor
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US Patent 7159045 Address management device
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US Patent 7159048 Direct memory access (DMA) transfer buffer processor
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US Patent 7159051 Free packet buffer allocation
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US Patent 7159055 Physical layer apparatus compliant to serial and parallel ATA interfaces
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US Patent 7159097 Apparatus and method for buffering instructions and late-generated related information using history of previous load/shifts
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US Patent 7159099 Streaming vector processor with reconfigurable interconnection switch
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US Patent 7159103 Zero-overhead loop operation in microprocessor having instruction buffer
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US Patent 7162619 Apparatus and method for densely packing a branch instruction predicted by a branch target address cache and associated target instructions into a byte-wide instruction buffer
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US Patent 7165126 Direct memory access device
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US Patent 7165129 Method and apparatus for self-tuning transaction batching
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US Patent 7165168 Microprocessor with branch target address cache update queue
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US Patent 7165169 Speculative branch target address cache with selective override by secondary predictor based on branch instruction type
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US Patent 7165184 Transferring data between differently clocked busses
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US Patent 7167933 Data transferring apparatus for transferring liquid ejection data and a liquid ejecting apparatus
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US Patent 7171458 Apparatus and method for managing configuration of computer systems on a computer network
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US Patent 7174444 Preventing a read of a next sequential chunk in branch prediction of a subject chunk
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US Patent 7177956 Ingress processing optimization via traffic classification and grouping
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US Patent 7177963 System and method for low-overhead monitoring of transmit queue empty status
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US Patent 7178009 Different register data indicators for each of a plurality of central processing units
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US Patent 7178013 Repeat function for processing of repetitive instruction streams
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US Patent 7181598 Prediction of load-store dependencies in a processing agent
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US Patent 7181599 Method and apparatus for autonomic detection of cache “chase tail” conditions and storage of instructions/data in “chase tail” data structure
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US Patent 7185070 Generic quality of service protocol and architecture for user applications in multiple transport protocol environments
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US Patent 7185120 Apparatus for period promotion avoidance for hubs
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US Patent 7185178 Fetch speculation in a multithreaded processor
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US Patent 7185186 Apparatus and method for resolving deadlock fetch conditions involving branch target address cache
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US Patent 7186063 Milling cutter
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US Patent 7188195 DMA slot allocation
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US Patent 7188197 Data transferring apparatus for transferring liquid ejection data and a liquid ejecting apparatus
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US Patent 7191162 FIFO interface for flag-initiated DMA frame synchro-burst operation
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US Patent 7191227 System for dynamically changing the communication means used for communication between two software agents
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US Patent 7191261 System and method to use unmodified operating system on diskless computer
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US Patent 7191264 Disk control apparatus
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US Patent 7191316 Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction stream
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US Patent 7197577 Autonomic input/output scheduler selector
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US Patent 7197581 Integrated circuit, device and method for inputting/outputting images
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US Patent 7197583 SDIO controller
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US Patent 7197627 Multiple processor arrangement for conserving power
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US Patent 7197630 Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation
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US Patent 7200689 Cacheable DMA
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US Patent 7200697 High speed data transfer between mainframe storage systems
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US Patent 7203775 System and method for avoiding deadlock
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US Patent 7203795 Digital recording, reproducing and recording/reproducing apparatus
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US Patent 7206871 Extending circuit for memory and transmitting-receiving device using extending circuit for memory
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US Patent 7206882 Triggered communication network for CANOpen networks
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US Patent 7216185 Buffering apparatus and buffering method
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US Patent 7234042 Identification bit at a predetermined instruction location that indicates whether the instruction is one or two independent operations and indicates the nature the operations executing in two processing channels
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US Patent 7249246 Methods and systems for maintaining information for locating non-native processor instructions when executing native processor instructions
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US Patent 7401205 High performance RISC instruction set digital signal processor having circular buffer and looping controls
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US Patent 7421517 Integrated circuit having multiple modes of operation
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US Patent 7480786 Methods and cores using existing PLD processors to emulate processors having different instruction sets and bus protocols
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US Patent 7631114 Serial communication device
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US Patent 7768767 Triggered pulsed ignition system and method
Edits on 5 Dec, 2021
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edited on 5 Dec, 2021
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Patent primary examiner of
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US Patent 7768767 Triggered pulsed ignition system and method
Edits on 3 Dec, 2021
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edited on 3 Dec, 2021
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US Patent 7631114 Serial communication device
Edits on 1 Dec, 2021
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edited on 1 Dec, 2021
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Golden AI
edited on 1 Dec, 2021
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Patent primary examiner of
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US Patent 7421517 Integrated circuit having multiple modes of operation
Edits on 30 Nov, 2021
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edited on 30 Nov, 2021
Edits on 22 Nov, 2021
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edited on 22 Nov, 2021
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edited on 22 Nov, 2021
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edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7216185 Buffering apparatus and buffering method
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7206882 Triggered communication network for CANOpen networks
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Golden AI
edited on 22 Nov, 2021
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7203795 Digital recording, reproducing and recording/reproducing apparatus
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7203775 System and method for avoiding deadlock
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7200697 High speed data transfer between mainframe storage systems
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7200689 Cacheable DMA
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Golden AI
edited on 22 Nov, 2021
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7197627 Multiple processor arrangement for conserving power
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7197583 SDIO controller
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
‌
US Patent 7197581 Integrated circuit, device and method for inputting/outputting images
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Golden AI
edited on 22 Nov, 2021
Edits made to:
Infobox (+1 properties)
Infobox
Patent primary examiner of
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US Patent 7197577 Autonomic input/output scheduler selector

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