Patent attributes
It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforward or a feedback control configuration to control critical dimension variation during semiconductor fabrication. By controlling critical dimensions through the adjustment of photoresist etch time, many advantages are achieved including a reduced lot-to-lot variation, an increased yield, and increased speed of the fabricated circuits. In one embodiment these advantages are achieved for polysilicon gate critical dimension control in microprocessor circuits. Polysilicon gate linewidth variability is reduced using a control method using either feedforward and feedback or feedback alone. In some embodiments, feedback control is implemented for controlling critical dimensions using photoresist each time as a manipulated variable. In an alternative embodiment, critical dimensions are controlled using RF power as a manipulated variable. A run-to-run control technique is used to drive the critical dimensions of integrated circuits to a set specification. In a run-to-run control technique a wafer test or measurement is made and a process control recipe is adjusted based on the result of the test or measurement on a run-by-run basis. The run-to-run control technique is applied to drive the critical dimensions of a polysilicon gate structure to a target specification. The run-to-run control technique is applied to drive the critical dimensions in an integrated circuit to a defined specification using photoresist etch time as a manipulated variable.
