US Patent 9929214 Nano-imprinted self-aligned multi-level processing method
Patent 9929214 was granted and assigned to Western Digital on March, 2018 by the United States Patent and Trademark Office.
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The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D cross-point memory arrays using a single nano-imprint lithography step and no photolithography are disclosed. The method includes imprinting a multilevel topography pattern, transferring the multilevel topography pattern to a substrate, filling the etched multilevel topography pattern with hard mask material, planarizing the hard mask material to expose a first portion of the substrate, etching a first trench in the first portion of the substrate, depositing a first plurality of layers in the first trench, planarizing the hard mask material to expose a second portion of the substrate, etching a second trench in the second portion of the substrate and depositing a second plurality of layers in the second trench. The method is repeated until a 4F2 3D cross-point memory array has been formed.
US Patent 09929214 Nano-imprinted self-aligned multi-level processing method US Patent 9929214 Nano-imprinted self-aligned multi-level processing method
US Patent 09929214 Nano-imprinted self-aligned multi-level processing method
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