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US Patent 9892771 Memory controller with dynamic core-transfer latency

Patent 9892771 was granted and assigned to Rambus on February, 2018 by the United States Patent and Trademark Office.

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Patent Applicant
Rambus
Rambus
1
Current Assignee
Rambus
Rambus
1
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
98927711
Patent Inventor Names
Robert E. Palmer1
William F. Stonecypher1
Date of Patent
February 13, 2018
1
Patent Application Number
151268681
Date Filed
March 24, 2015
1
Patent Citations Received
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US Patent 11763865 Signal receiver with skew-tolerant strobe gating
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US Patent 12062413 Signal receiver with skew-tolerant strobe gating
2
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US Patent 11749323 Signal receiver with skew-tolerant strobe gating
Patent Primary Examiner
‌
James G Norman
1
Patent abstract

In a memory controller having a controller core and a physical signaling interface, the controller core outputs a request for read data to the physical signaling interface specifying one of at least two memory components from which the read data is to be retrieved. In response to the request for read data, the physical signaling interface outputs a memory read request to the specified memory component, receives the read data from the specified memory component, and transfers the read data to the controller core at either a first time or a second time according to whether the specified memory component is a first memory component or second memory component of the at least two memory components.

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