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US Patent 9842428 Dynamically optimized deferred rendering pipeline

Patent 9842428 was granted and assigned to SAMSUNG ELECTRONICS CO., LTD. on December, 2017 by the United States Patent and Trademark Office.

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Current Assignee
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
9842428
Patent Inventor Names
Zhenghong Wang2
Date of Patent
December 12, 2017
Patent Application Number
14679720
Date Filed
April 6, 2015
Patent Citations Received
‌
US Patent 11977922 Resource reuse for pipeline workloads
1
Patent Primary Examiner
‌
Devona E. Faulk
Patent abstract

A method for dynamically configuring a graphics pipeline system. The method includes determining an optimal pipeline based on: estimating one or more of memory power consumption and computation power consumption of storing and regenerating intermediate results based on graphics state information and one or more factors; determining granularity for the optimal graphics pipeline configuration based on the graphics state information and the one or more factors; collecting runtime information for primitives from graphics pipeline hardware including factors from tessellation or using graphics state information for determining geometry expansion at an output of one or more shader stages; and determining intermediate results to save from a previous processing pass by comparing memory power consumption needed to save the intermediate results with computation power as well as memory power needed for regenerating the intermediate results in one or more later tile rendering passes.

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