US Patent 9837132 High capacity memory system

The embodiments described herein describe technologies for memory systems. One implementation of a memory module includes multiple device sites coupled to the a data query (DQ) buffer component via data lines and coupled to a command and address (CA) buffer component via chip select (CS) lines. A first number of the CS lines between the CA buffer component and any combination of two or more of the multiple device sites is greater than a second number of the CS lines between the CA buffer component and a single one of the multiple device sites.