US Patent 9804975 Hardware-enforced prevention of buffer overflow

An apparatus having processing circuitry configured to execute applications involving access to memory may include a CPU and a cache controller. The CPU may be configured to access cache memory for execution of an application. The cache controller may be configured to provide an interface between the CPU and the cache memory. The cache controller may include a bitmask to enable the cache controller to employ a two-level data structure to identify memory exploits using hardware. The two-level data structure may include a page level protection mechanism, and a sub-page level protection mechanism.