US Patent 9766410 Wafer-level testing of photonic integrated circuits with optical IOs

Techniques for forming a photonic integrated circuit having a facet coupler and a surface coupler are described. The photonic integrated circuit may be on a wafer, which may be diced to form an integrated device. The facet coupler may be positioned proximate to an edge of the integrated device, and the surface coupler may be positioned on a surface of the integrated device. The surface coupler may allow for evaluation and assessment of the circuit's performance, which may facilitate wafer-level testing of the circuit and diagnosis of the circuit before and after packaging.