US Patent 9761559 Semiconductor package and fabrication method thereof

A semiconductor package includes a first logic die, a second logic die disposed in close proximity to the first logic die, a bridge memory die coupled to both the first logic die and the second logic die, a redistribution layer (RDL) structure coupled to the first logic die and the second logic die, and a molding compound at least partially encapsulating the first logic die, the second logic die, and the bridge memory die. The first logic die and the second logic die are coplanar.