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US Patent 9711501 Interlayer via

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
September 26, 2016
Date of Patent
July 18, 2017
Patent Application Number
15276333
Patent Citations Received
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US Patent 12107085 Interconnect techniques for electrically connecting source/drain regions of stacked transistors
0
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US Patent 12080714 Buried local interconnect between complementary field-effect transistor cells
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US Patent 12086524 Semiconductor device having more similar cell densities in alternating rows
0
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US Patent 11881452 Device layer interconnects
0
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US Patent 11887988 Thin film transistor structures with regrown source and drain
0
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US Patent 11929320 Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication
0
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US Patent 11935929 High aspect ratio shared contacts
0
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US Patent 11996404 Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material
0
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US Patent 12002805 Local vertical interconnects for monolithic stack transistors
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
9711501
Patent Primary Examiner
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Ngan Ngo

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