Patent attributes
The asynchronous circuit includes an input channel, a divergence operator connecting the input channel to a plurality of intermediate channels, a convergence operator gathering the intermediate channels into a single output channel, a main sequencer including a plurality of sequentially-activated control channels, each intermediate channel being associated to a control channel, and a switch arranged in a request path of one of the intermediate channels and connected to the last active control channel. The circuit further includes a memory circuit, arranged in each of the other intermediate channels, connected to the associated control channel and configured to transmit the request signal of the associated intermediate channel to the output channel and to modify an output state of the associated intermediate channel, by means of the main sequencer, without requiring any state change of the input channel.
