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US Patent 9425126 Dummy structure for chip-on-wafer-on-substrate
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Patent
Date Filed
May 29, 2014
Date of Patent
August 23, 2016
Patent Application Number
14289819
Patent Citations Received
US Patent 12136619 Methods of manufacturing three-dimensional integrated circuit structures
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US Patent 12113031 Semiconductor device and method of making the same
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US Patent 12119276 Package structure with protective lid
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US Patent 12119292 Semiconductor device and method of manufacture
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US Patent 12125755 Chip package structure with cavity in interposer
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US Patent 12125782 Semiconductor structure and method of forming the same
0
US Patent 12125798 Semiconductor package and method
0
US Patent 12125812 Integrated circuit packages and methods of forming the same
0
US Patent 12125819 Die on die bonding structure
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US Patent 12131974 Semiconductor package and method of manufacturing semiconductor package
0
•••
Patent Inventor Names
Pei-Ching Kuo
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Jun-Lin Yeh
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Ku-Feng Yang
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Li-Han Hsu
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Wei-Cheng Wu
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Wen-Chih Chiou
0
Yi-Hsiu Chen
0
Yung-Chi Lin
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
9425126
Patent Primary Examiner
Matthew Reames
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