US Patent 9330983 CMOS NFET and PFET comparable spacer width

A method including forming a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET device) each having sidewall spacers on opposite sidewalls of a dummy gate, conformally forming a first liner on the nFET device and depositing a fill material directly on the first liner of the nFET device, protecting the nFET device while growing an epitaxy in a source drain region of the pFET device, conformally forming a second liner above and in direct contact with the pFET device, including the epitaxy in the source drain regions of the pFET device, and along a vertical sidewall of a remaining portion of the fill material above the nFET device, depositing a first inter level dielectric above the second liner, and protecting the pFET device and the first inter level dielectric while growing a second epitaxy in a source drain region of the nFET device.