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US Patent 9281305 Transistor device structure

Patent 9281305 was granted and assigned to National Applied Research Laboratories on March, 2016 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Patent Applicant
National Applied Research Laboratories
National Applied Research Laboratories
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Current Assignee
National Applied Research Laboratories
National Applied Research Laboratories
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
92813050
Patent Inventor Names
Chang-Hong Shen0
Chih-Chao Yang0
Jia-Min Shieh0
Szu-Hung Chen0
Tung-Ying Hsieh0
Wen-Hsien Huang0
Date of Patent
March 8, 2016
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Patent Application Number
145613770
Date Filed
December 5, 2014
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Patent Citations Received
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US Patent 12087750 Stacked-substrate FPGA semiconductor devices
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US Patent 11782057 Ic with graphene fet sensor array patterned in layers above circuitry formed in a silicon based cmos wafer
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US Patent 11921112 Chemically-sensitive field effect transistors, systems, and methods for manufacturing and using the same
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Patent Primary Examiner
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Michele Fan
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Patent abstract

A transistor device structure includes a substrate, a first transistor layer and a second transistor layer. The second transistor layer is disposed between the substrate and the first transistor layer. The first transistor layer includes an insulating structure and a first transistor unit. The insulating structure is disposed on the second transistor layer and has a protruding portion. The first transistor unit includes a gate structure, a source/drain structure, an embedded source/drain structure and a channel. The source/drain structure is disposed beside the gate structure and over the insulating structure. The embedded source/drain structure is disposed underneath the source/drain structure and in the insulating structure. The channel is defined between the protruding portion and the gate structure.

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