US Patent 9268552 Patching improvement for executables in memory constrained devices

A processing device determines a memory layout for an executable comprising a plurality of functions and data, wherein the memory layout is determined based on one or more object files. The processing device updates the memory layout by inserting an unused memory region between a first function and a second function of the plurality of functions in the memory layout, wherein the first function and the second function have adjacent memory locations in the memory layout prior to insertion of the unused memory region. The processing device resolves references between the plurality of functions. The processing device then generates an executable comprising the plurality of functions and the data arranged in accordance with the memory layout, the executable having the resolved references.