US Patent 9263144 Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first sub-array including a plurality of first memory cells; a second sub-array including a plurality of second memory cells; a first bit line electrically connected to a first group of the first memory cells; a second bit line electrically connected to a first group of the second memory cells; a bit line connection unit configured to connect the first bit line and the second bit line; a first sense amplifier configured to receive a first voltage from either of the first bit line and the second bit line in a read operation, and transfer a second voltage either of the first bit line and the second bit line in a write operation; a first source line electrically connected to the first memory cells; a second source line electrically connected to the second memory cells; and a source line driver configured to apply voltages to the first source line and the second source line.