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US Patent 9070599 Array substrate, manufacturing method thereof and display device

Patent 9070599 was granted and assigned to BOE Technology Group Co., Ltd. on June, 2015 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
BOE Technology Group Co., Ltd.
BOE Technology Group Co., Ltd.
Current Assignee
BOE Technology Group Co., Ltd.
BOE Technology Group Co., Ltd.
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
9070599
Patent Inventor Names
Seongyeol Yoo0
Heecheol Kim0
Seungjin Choi0
Youngsuk Song0
Date of Patent
June 30, 2015
Patent Application Number
14361396
Date Filed
October 31, 2013
Patent Citations Received
‌
US Patent 12014696 Display substrate, display panel and display device, of each of which a pixel electrode having a hollowed-out structure with a preset size
0
Patent Primary Examiner
‌
Steven J Fulk
Patent abstract

An array substrate, a manufacturing method thereof and a display device are provided, and the array substrate comprises: a substrate (1); a plurality of data lines (16), formed on the substrate and extending in a first direction; a plurality of gate lines (15), formed on the substrate (1), crossing the plurality of data lines (15), and extending in a second direction perpendicular to the first direction; a plurality of pixel regions, defined by the plurality of gate lines (15) and the plurality of data lines (15) crossing each other and arranged in a matrix form, wherein each of the pixel regions is provided with a thin film transistor and a pixel electrode (12), wherein, the thin film transistor comprises: a gate electrode (2), connected with one of the plurality of gate lines (15); a gate insulating layer (3), provided above the gate line (15) and the gate electrode (2); an active layer (5), formed on the gate insulating layer (3) and disposed corresponding to the gate electrode (2); a drain electrode (8) and a source electrode (9), disposed opposite to each other above the active layer (5) and having a channel region of the thin film transistor therebetween; a filling layer (4), provided between the gate electrode (2) and the gate line (15) connected with the gate electrode, and the drain and source electrodes (8) and (9); and a passivation layer (10), provided on the source electrode (9), the drain electrode (8) and the active layer (5), wherein at a position directly facing the gate line (15), the passivation layer (10) is provided with a passivation layer through hole (11) configured to perform a connection between the drain electrode (8) and the pixel electrode (12).

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