US Patent 8958246 Vertically foldable memory array structure

A vertically foldable memory array structure is provided, comprising: a memory module distributed in columns and rows, comprising: a drain selection transistor; a bottom connecting line and a source selection transistor; and a plurality of memory cell transistors connected between the drain selection transistor and the bottom connecting line and between the source selection transistor and the bottom connecting line, a drain of each drain selection transistor is connected to a bit line, a drain of a drain selection transistor in a Mth vertically foldable memory module in a Nth column and a source of a source selection transistor in a (M−1)th memory module in a (N+1)th column are connected to a same bit line, gates of the drain selection transistors and the source selection transistors in all the memory modules in the Nth column are connected to a same drain selection line and a same source selection line.