Patent attributes
The present invention relates to a data processing device and a data processing method capable of improving the resistance to data error. In a case where an LDPC code having a code length of 4,320 bits is mapped into 16 signal points, when a code bit of 4×2 bits and the (#i+1)-th bit from the most significant bit of symbol bits of 4×2 bits of two consecutive symbols are bits b#i and y#i, a demultiplexer performs an interchange process in which b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y1, b3 is allocated to y6, b4 is allocated to y2, b5 is allocated to y5, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 1/2, and b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y5, b3 is allocated to y2, b4 is allocated to y1, b5 is allocated to y6, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 7/12, 2/3, and 3/4. The present invention, for example, can be applied to a transmission system transmitting an LDPC code and the like.
