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US Patent 8683285 Parallel packetized interconnect with simplified data link layer

Patent 8683285 was granted and assigned to PLX Technology (company) on March, 2014 by the United States Patent and Trademark Office.

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Patent
Patent

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Current Assignee
PLX Technology (company)
PLX Technology (company)
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
8683285
Date of Patent
March 25, 2014
Patent Application Number
12980602
Date Filed
December 29, 2010
Patent Primary Examiner
‌
Joshua P Lottich
Patent abstract

In a first embodiment of the present invention, a method for error-correcting in a parallel interconnect transmitting device is provided, the method comprising: detecting a frame transition in a transmission from the transmitting device to a parallel interconnect receiving device; tracking time between the frame transition and a transition of a response signal corresponding to the frame transition received from the receiving device; detecting an error in the transmission; and restarting a portion of the transmission in response to the error, wherein the size of the portion of the transmission to restart is based upon the tracked time between the frame transition and the transition of a response signal corresponding to the frame transition.

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