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US Patent 8670261 Stub minimization using duplicate sets of signal terminals
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Patent
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Date Filed
April 9, 2013
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Date of Patent
March 11, 2014
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Patent Application Number
13859271
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Patent Citations Received
US Patent 12112113 Complementary die-to-die interface
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US Patent 11803471 Scalable system on a chip
US Patent 11934313 Scalable system on a chip
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US Patent 11990382 Fine pitch BVA using reconstituted wafer with area array accessible for testing
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US Patent RE49987 Multiple plated via arrays of different wire heights on a same substrate
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US Patent 12007895 Scalable system on a chip
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Patent Inventor Names
Frank Lambrecht
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Richard Dewitt Crisp
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Wael Zohni
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Belgacem Haba
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
8670261
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Patent Primary Examiner
Vu Le
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