Patent attributes
A resistive random access memory cell is formed on a semiconductor substrate. First and second diffused regions are disposed in the semiconductor substrate. A polysilicon gate is disposed above the first and second diffused regions. A first contact connects the first diffused region with a region of a first metal layer. A first interlayer dielectric layer is formed over the first metal layer and includes first and second vias, each including conductive plugs connected to the region of the first metal layer. First and second resistive random access memory devices formed over the first interlayer dielectric layer have first and second terminals, and include a dielectric layer and an ion source layer. The first terminals of the first and second resistive random access memory devices are coupled to the first metal layer by the first and second conductive plugs.
