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US Patent 8345441 Stub minimization for multi-die wirebond assemblies with parallel windows

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Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
8345441
Date of Patent
January 1, 2013
Patent Application Number
13337575
Date Filed
December 27, 2011
Patent Citations Received
‌
US Patent 12107042 Localized high density substrate routing
3
‌
US Patent 11984396 Localized high density substrate routing
4
Patent Primary Examiner
‌
Tuan T Dinh
Patent abstract

A microelectronic assembly can include first and second microelectronic packages mounted to respective first and second opposed surfaces of a circuit panel. Each microelectronic package can include a substrate having first and second apertures extending between first and second surfaces thereof, first and second microelectronic elements each having a surface facing the first surface of the substrate and a plurality of contacts at the surface of the respective microelectronic element aligned with at least one of the apertures, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between the contacts of each microelectronic element and the terminals. The apertures of each substrate can have first and second parallel axes extending in directions of the lengths of the respective apertures. The terminals of each microelectronic package can be configured to carry all of the address signals transferred to the respective microelectronic package.

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