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US Patent 8190820 Optimizing concurrent accesses in a directory-based coherency protocol

Patent 8190820 was granted and assigned to Intel on May, 2012 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Current Assignee
Intel
Intel
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
81908200
Patent Inventor Names
Akhilesh Kumar0
Hariharan Thantry0
Seungjoon Park0
Date of Patent
May 29, 2012
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Patent Application Number
121577920
Date Filed
June 13, 2008
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Patent Citations Received
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US Patent 11803471 Scalable system on a chip
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US Patent 11947457 Scalable cache coherency protocol
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US Patent 11934313 Scalable system on a chip
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US Patent 12007895 Scalable system on a chip
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US Patent 11868258 Scalable cache coherency protocol
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Patent Primary Examiner
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Michael Krofcheck
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Patent abstract

In one embodiment, the present invention includes a directory to aid in maintaining control of a cache coherency protocol. The directory can be coupled to multiple caching agents via an interconnect, and be configured to store a entries associated with cache lines. The directory also includes logic to determine a time delay before the directory can send a concurrent snoop request. Other embodiments are described and claimed.

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