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US Patent 8159053 Flat leadless packages and stacked leadless package assemblies

Patent 8159053 was granted and assigned to Vertical Circuits on April, 2012 by the United States Patent and Trademark Office.

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Is a
Patent
Patent

Patent attributes

Current Assignee
Vertical Circuits
Vertical Circuits
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
8159053
Patent Inventor Names
Simon J. S. McElrea0
Jeffrey S. Leal0
Lawrence Douglas Andrews, Jr.0
Date of Patent
April 17, 2012
Patent Application Number
12892739
Date Filed
September 28, 2010
Patent Primary Examiner
‌
Roy K Potter
Patent abstract

A flat leadless package includes at least one die mounted onto a leadframe and electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, an assembly includes stacked leadless packages electrically connected to leads using an electrically conductive polymer or an electrically conductive ink. Also, a package module includes an assembly of stacked leadless packages mounted on a support and electrically connected to circuitry in the support using an electrically conductive polymer or an electrically conductive ink.

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