US Patent 8155308 Advanced encryption system hardware architecture

A cryptographic device comprises a first pipeline stage, a pipeline register, and a second pipeline stage. The first pipeline stage comprises a first byte substitution module that performs mathematical operations on a received byte and outputs an intermediate value based on the mathematical operations. The pipeline register stores the intermediate value. The second pipeline stage comprises a second byte substitution module and a column mixing module. The second byte substitution module generates a replacement byte corresponding to the received byte based on mathematical operations performed on the stored intermediate value. The column mixing module transforms groups of four bytes of a plurality of replacement bytes including the replacement byte.