A matching circuit including a main matching block 51 inserted in a signal path and a series matching block 522, one end of which is connected to the main matching block 51, in which one end of a series connection of a switch 542 and a parallel matching block 532 is connected to the signal path at the other end of the series matching block 522 and impedance matching between input/output is performed at any one of two frequencies by setting the switch to ON/OFF.