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US Patent 8048721 Method for filling multi-layer chip-stacked gaps

Patent 8048721 was granted and assigned to Powertech Technology on November, 2011 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
1

Patent attributes

Current Assignee
‌
Powertech Technology
1
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
80487211
Patent Inventor Names
Hung-Hsin Hsu1
Wei-Chih Chien1
Date of Patent
November 1, 2011
1
Patent Application Number
127270331
Date Filed
March 18, 2010
1
Patent Citations Received
‌
US Patent 11984337 Device for self-assembling semiconductor light-emitting diodes
2
Patent Primary Examiner
‌
Caridad Everhart
1
Patent abstract

A method for filling multi-layer chip-stacked gaps is revealed, primarily comprising the steps as below. Firstly, a chip-stacked assembly is provided, comprising a substrate and a plurality of chips vertically stacked on the substrate where at least a first underfilling gap is formed between each two adjacent ones of the stacked chips with a height difference from the substrate. Then, the chip-stacked assembly is flipped and dipped into an underfilling material where the underfilling material is disposed in a storage tank in a flowing state to completely fill the first underfilling gap. Then, the chip-stacked assembly is taken out. Finally, the chip-stacked assembly is heated to cure the underfilling material filled in the first underfilling gap. Accordingly, multi-layer chip-stacked gaps with different heights can be simultaneously filled at one single step. The conventional underfilling difficulty of multi-layer chip-stacked gaps can be solved leading to higher productivity.

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