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US Patent 8046524 Managing processing delays in an isochronous system

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
80465241
Patent Inventor Names
Yosief Ataklti1
Shai Traister1
J. James Tringali1
Sergey A. Gorobets1
Date of Patent
October 25, 2011
1
Patent Application Number
118647931
Date Filed
September 28, 2007
1
Patent Citations Received
‌
US Patent 12093533 Memory management of nonvolatile discrete namespaces
2
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US Patent 11704237 Storage system with multiplane segments and query based cooperative flash management
3
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US Patent 11748257 Host, storage system, and methods with subdivisions and query based write operations
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US Patent 11762766 Storage device with erase unit level address mapping
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US Patent 11868247 Storage system with multiplane segments and cooperative flash management
4
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US Patent 11907134 Nonvolatile memory controller supporting variable configurability and forward compatibility
5
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US Patent 11914523 Hierarchical storage device with host controlled subdivisions
6
Patent Primary Examiner
‌
Edward J Dudek, Jr.
1
Patent abstract

Command cycles incorporate mechanisms to inform a host processor in advance of a need to service the memory so that the host can respond when it suits the host, but in time for the service to be performed before a catastrophic failure. The regular host cycle need not be interrupted for such notification.

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