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US Patent 8028186 Skew management in an interconnection system

Patent 8028186 was granted and assigned to Violin Memory on September, 2011 by the United States Patent and Trademark Office.

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Patent

Patent attributes

Current Assignee
Violin Memory
Violin Memory
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
8028186
Patent Inventor Names
Jon C. R. Bennett0
Date of Patent
September 27, 2011
Patent Application Number
11975269
Date Filed
October 17, 2007
Patent Citations Received
‌
US Patent 11963299 Load reduced memory module
0
Patent Primary Examiner
‌
Matthew Spittle
Patent abstract

An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

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