Patent attributes
A dynamic random access memory (DRAM) controller may comprise two sub-controllers, each capable of handling a respective N-bit interface (e.g. 64-bit interface). Each sub-controller may also be configurable to be (2*N)-bit (e.g. 128-bit) capable with respect to control logic, for controlling a logical 128-bit data path. In ganged mode, each sub-controller may logically operate as if it were handling data in 128-bit chunks, (i.e. handling the entire 128-bit data path), while actual full bandwidth may be achieved by having one of the sub-controllers operate on commands and a first N-bit portion of each (2*N)-bit chunk of data, and having the other sub-controller operate on a “copy” of the commands with a corresponding remaining N-bit portion of each (2*N)-bit chunk of data. Once the basic input/output system (BIOS) has configured and initialized the two DRAM controllers to operate in ganged mode, the BIOS and all software may no longer need to be aware that two memory controllers are used to access a single (2*N)-bit wide channel.
