Patent attributes
The object of the present invention is to provide a data decision apparatus and an error measurement apparatus which can set the phase of the clock to the optimum state with respect to the data signal without continuously sweeping of the phase, and can keep the state for a long time. The data decision apparatus according to the present invention comprises a delay device (34) for delaying a data signal (Dc) outputted from a decision device (31) by one bit, a first phase detector (35) for detecting a phase difference between a data signal (Db) to be inputted to the decision device (31) and the data signal (Dc) outputted from the decision device (31), a second phase detector (36) for detecting a phase difference between the data signal (Dc) outputted from the decision device (31) and a data signal (Dd) outputted from the delay device (34), a third phase detector (37) for outputting a base voltage with respect to the output values of the first and second phase detectors (35 and 36), and a phase controller (38) for controlling a phase shift amount of a variable delay device (32) to equalize an output value (P1) of the first phase detector (35) to a center value between an output value (P2) of the second phase detector (36) and the base voltage (P3).
