US Patent 8004913 Redundancy architecture for an integrated circuit memory

An integrated circuit memory includes multiple memory banks grouped into repair groups Group0, Group1. One memory has redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.