Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Tsu-Jae King Liu0
Date of Patent
August 9, 2011
Patent Application Number
12250463
Date Filed
October 13, 2008
Patent Primary Examiner
Patent abstract
A memory cell includes a pull-up element that exhibits a refresh behavior that is dependent on the data value stored in the memory cell. The pull-up element is an NDR FET connected between a high voltage source and a storage node of the memory cell. The NDR FET receives a pulsed gate bias signal, wherein each pulse turns on the NDR FET when a logic HIGH value is stored at the storage node, and further wherein each pulse does not turn on the NDR FET when a logic LOW value is stored at the storage node. In this fashion a DRAM cell (and device) can be operated without a separate refresh cycle.
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